void mt7996_wfsys_reset(struct mt7996_dev *dev)
{
- mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
- msleep(20);
+ if (!is_mt7990(&dev->mt76)) {
+ mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
+ msleep(20);
+
+ mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
+ msleep(20);
+
+ return;
+ }
- mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
+ if (!dev->recovery.hw_full_reset)
+ return;
+
+ mt76_set(dev, MT_WF_SUBSYS_RST,
+ MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT |
+ MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT |
+ MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT);
+ mt76_rmw(dev, MT_WF_SUBSYS_RST,
+ MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE,
+ u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE));
+ mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK);
+ mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST);
msleep(20);
+
+ if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000))
+ return;
+
+ dev_err(dev->mt76.dev, "wfsys reset fail\n");
}
static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev)
#define MT_HW_REV 0x70010204
#define MT_HW_REV1 0x8a00
+#define MT_WF_L05_RST 0x70028550
+#define MT_WF_L05_RST_WF_RST_MASK GENMASK(4, 0)
+
#define MT_WF_SUBSYS_RST 0x70028600
+#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST BIT(0)
+#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT BIT(5)
+#define MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT BIT(6)
+#define MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT BIT(16)
+#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE GENMASK(15, 8)
/* PCIE MAC */
#define MT_PCIE_MAC_BASE 0x74030000