The following instructions were introduced in the Power ISA 2.05

(i.e., POWER6) - lfdp - stfdp - lfdpx - stfdpx These instructions were promptly
deprecated (phased out) in ISA 2.06 (i.e., POWER7). Recent updates in binutils
no longer supports these instructions unless the assembler is invoked with
'-mpower6'. When 'make check' is run on valgrind when using such a newer
binutils and running on a ppc64 system newer than POWER6, you get the
following build error:
y
pc64_linux=1 -DVGPV_ppc64_linux_vanilla=1 -DVGA_SEC_ppc32=1 -DVGP_SEC_ppc64_linux=1 -Winline -Wall -Wshadow -g -Winline -Wall -Wshadow -g -I../../../include -m64 -Wno-long-long -Wwrite-strings -fno-stack-protector -Wno-write-strings -MT power_ISA2_05-power_ISA2_05.o -MD -MP -MF .deps/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo './'`power_ISA2_05.c
/tmp/cciGIkGG.s:Assembler messages:
/tmp/cciGIkGG.s:387: Error: operand out of domain (31 is not a multiple of 4)
/tmp/cciGIkGG.s:387: Error: syntax error; found `,', expected `('
/tmp/cciGIkGG.s:387: Error: junk at end of line: `,9'
/tmp/cciGIkGG.s:478: Error: operand out of domain (31 is not a multiple of 4)
/tmp/cciGIkGG.s:478: Error: syntax error; found `,', expected `('
/tmp/cciGIkGG.s:478: Error: junk at end of line: `,9'
make[2]: *** [power_ISA2_05-power_ISA2_05.o] Error 1
make[2]: Leaving directory `/tmp/Valgrind_review/valgrind_ISA2_05/memcheck/tests/ppc64'
make[1]: *** [check-am] Error 2
make[1]: Leaving directory `/tmp/Valgrind_review/valgrind_ISA2_05/memcheck/tests/ppc64' make: *** [check-recursive] Error 1

This patch fixes the problem by adding a configure check to determine if these
phased out instructions are supported by the binutils, and the result of that
configure check is used to decide whether or not to compile in the source for
testing these instructions.

Bugzilla 323116

committed by Carl Love, carll@us.ibm.com

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13490

diff --git a/configure.in b/configure.in
index 6ac32b041020a28bb87e300495f796e306582d3b..5cf28a17535d06d41b309c0bd7b2937c861ccd97 100644 (file)
--- a/configure.in
+++ b/configure.in
@@ -1771,6 +1771,28 @@ if test x$ac_have_as_ppc_mftocrf = xyes ; then
 fi
 
 
+# does the ppc assembler support "lfdp" and other phased out floating point insns?
+AC_MSG_CHECKING([if ppc32/64 asm supports phased out floating point instructions])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+  do { typedef struct {
+      double hi;
+      double lo;
+     } dbl_pair_t;
+     dbl_pair_t dbl_pair[3];
+     __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
+   } while (0)
+]])], [
+ac_have_as_ppc_fpPO=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_ppc_fpPO=no
+AC_MSG_RESULT([no])
+])
+if test x$ac_have_as_ppc_fpPO = xyes ; then
+  AC_DEFINE(HAVE_AS_PPC_FPPO, 1, [Define to 1 if as supports floating point phased out category.])
+fi
+
 CFLAGS=$safe_CFLAGS
 
 # does the x86/amd64 assembler understand SSE3 instructions?

diff --git a/memcheck/tests/ppc32/Makefile.am b/memcheck/tests/ppc32/Makefile.am
index 40033fc315f728b56330ab19f1b0da9c14841f39..bd70eea67145254bbcc401f1d9f8032076b0b8ca 100644 (file)
--- a/memcheck/tests/ppc32/Makefile.am
+++ b/memcheck/tests/ppc32/Makefile.am
@@ -4,7 +4,8 @@ include $(top_srcdir)/Makefile.tool-tests.am
 dist_noinst_SCRIPTS = filter_stderr
 
 EXTRA_DIST = $(noinst_SCRIPTS) \
-       power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+       power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
+       power_ISA2_05.stdout.exp_Without_FPPO
 
 check_PROGRAMS = \
        power_ISA2_05

diff --git a/memcheck/tests/ppc32/power_ISA2_05.c b/memcheck/tests/ppc32/power_ISA2_05.c
index 017845261e983fd4cde55710b91bf95945e394d9..3736c274ad8354b33bbbef9666bf0cf86a6f5492 100644 (file)
--- a/memcheck/tests/ppc32/power_ISA2_05.c
+++ b/memcheck/tests/ppc32/power_ISA2_05.c
@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <config.h>
 
 double foo = -1.0;
 double FRT1;
@@ -65,9 +66,15 @@ void test_lfiwax()
 ** FPp = leftmost 64 bits stored at DS(RA)
 ** FPp+1= rightmost 64 bits stored at DS(RA)
 ** FPp must be an even float register
+**
+** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out"
+** category in ISA 2.06 (i.e., POWER7 timeframe).  If valgrind and its
+** testsuite are built with -mcpu=power7 (or later), then the assembler will
+** not recognize those phased out instructions.
 */
 void test_double_pair_instrs()
 {
+#ifdef HAVE_AS_PPC_FPPO
    typedef struct {
       double hi;
       double lo;
@@ -122,6 +129,7 @@ void test_double_pair_instrs()
    __asm__ volatile ("stfdpx 10, 20, 21");
    printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
           FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
+#endif
 }
 
 

diff --git a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO
new file mode 120000 (symlink)
index 0000000..da5c109
--- /dev/null
+++ b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO
@@ -0,0 +1 @@
+../ppc64/power_ISA2_05.stdout.exp_Without_FPPO
\ No newline at end of file

diff --git a/memcheck/tests/ppc64/Makefile.am b/memcheck/tests/ppc64/Makefile.am
index a18afd76fcdd743be706bf33d1d937f1281a0c1a..96eb5760fbf9b13152461ec9c36c14bf26748467 100644 (file)
--- a/memcheck/tests/ppc64/Makefile.am
+++ b/memcheck/tests/ppc64/Makefile.am
@@ -4,7 +4,8 @@ include $(top_srcdir)/Makefile.tool-tests.am
 dist_noinst_SCRIPTS = filter_stderr
 
 EXTRA_DIST = $(noinst_SCRIPTS) \
-       power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+       power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
+       power_ISA2_05.stdout.exp_Without_FPPO
 
 check_PROGRAMS = \
        power_ISA2_05

diff --git a/memcheck/tests/ppc64/power_ISA2_05.c b/memcheck/tests/ppc64/power_ISA2_05.c
index 8c0eab99a67e3962e2eeba6d22e4dfcaf8270447..f552dc4212591155a3cb7206f68bab7a5537ec9e 100644 (file)
--- a/memcheck/tests/ppc64/power_ISA2_05.c
+++ b/memcheck/tests/ppc64/power_ISA2_05.c
@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <config.h>
 
 double foo = -1.0;
 double FRT1;
@@ -63,9 +64,16 @@ void test_lfiwax()
 ** FPp = leftmost 64 bits stored at DS(RA)
 ** FPp+1= rightmost 64 bits stored at DS(RA)
 ** FPp must be an even float register
+**
+** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out"
+** category in ISA 2.06 (i.e., POWER7 timeframe).  If valgrind and its
+** testsuite are built with -mcpu=power7 (or later), then the assembler will
+** not recognize those phased out instructions.
+**
 */
 void test_double_pair_instrs()
 {
+#ifdef HAVE_AS_PPC_FPPO
    typedef struct {
       double hi;
       double lo;
@@ -120,6 +128,7 @@ void test_double_pair_instrs()
    __asm__ volatile ("stfdpx 10, 20, 21");
    printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
           FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
+#endif
 }
 
 

diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO
new file mode 100644 (file)
index 0000000..1945526
--- /dev/null
+++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO
@@ -0,0 +1,119 @@
+lwarx => 0
+ldarx => bad0beef
+fcpsgn sign=10.101010, base=11.111111 => 11.111111
+fcpsgn sign=10.101010, base=-0.000000 => 0.000000
+fcpsgn sign=10.101010, base=0.000000 => 0.000000
+fcpsgn sign=10.101010, base=-11.111111 => 11.111111
+fcpsgn sign=-0.000000, base=11.111111 => -11.111111
+fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
+fcpsgn sign=-0.000000, base=0.000000 => -0.000000
+fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
+fcpsgn sign=0.000000, base=11.111111 => 11.111111
+fcpsgn sign=0.000000, base=-0.000000 => 0.000000
+fcpsgn sign=0.000000, base=0.000000 => 0.000000
+fcpsgn sign=0.000000, base=-11.111111 => 11.111111
+fcpsgn sign=-10.101010, base=11.111111 => -11.111111
+fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
+fcpsgn sign=-10.101010, base=0.000000 => -0.000000
+fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
+lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
+prtyd (0) => parity=0
+prtyw (0) => parity=0
+prtyd (1) => parity=1
+prtyw (1) => parity=1
+prtyd (2) => parity=0
+prtyw (2) => parity=0
+prtyd (3) => parity=1
+prtyw (3) => parity=1
+prtyd (4) => parity=0
+prtyw (4) => parity=0
+prtyd (5) => parity=1
+prtyw (5) => parity=1
+prtyd (6) => parity=0
+prtyw (6) => parity=0
+prtyd (7) => parity=1
+prtyw (7) => parity=1
+prtyd (8) => parity=0
+prtyw (8) => parity=0
+prtyd (9) => parity=1
+prtyw (9) => parity=1
+prtyd (a) => parity=0
+prtyw (a) => parity=0
+prtyd (b) => parity=1
+prtyw (b) => parity=1
+prtyd (c) => parity=0
+prtyw (c) => parity=0
+prtyd (d) => parity=1
+prtyw (d) => parity=1
+prtyd (e) => parity=0
+prtyw (e) => parity=0
+prtyd (f) => parity=1
+prtyw (f) => parity=1
+prtyd (10) => parity=0
+prtyw (10) => parity=0
+prtyd (11) => parity=1
+prtyw (11) => parity=1
+prtyd (12) => parity=0
+prtyw (12) => parity=0
+prtyd (13) => parity=1
+prtyw (13) => parity=1
+prtyd (14) => parity=0
+prtyw (14) => parity=0
+prtyd (15) => parity=1
+prtyw (15) => parity=1
+prtyd (16) => parity=0
+prtyw (16) => parity=0
+prtyd (17) => parity=1
+prtyw (17) => parity=1
+prtyd (18) => parity=0
+prtyw (18) => parity=0
+prtyd (19) => parity=1
+prtyw (19) => parity=1
+prtyd (1a) => parity=0
+prtyw (1a) => parity=0
+prtyd (1b) => parity=1
+prtyw (1b) => parity=1
+prtyd (1c) => parity=0
+prtyw (1c) => parity=0
+prtyd (1d) => parity=1
+prtyw (1d) => parity=1
+prtyd (1e) => parity=0
+prtyw (1e) => parity=0
+prtyd (1f) => parity=1
+prtyw (1f) => parity=1
+prtyd (20) => parity=0
+prtyw (20) => parity=0
+prtyd (21) => parity=1
+prtyw (21) => parity=1
+prtyd (22) => parity=0
+prtyw (22) => parity=0
+prtyd (23) => parity=1
+prtyw (23) => parity=1
+prtyd (24) => parity=0
+prtyw (24) => parity=0
+prtyd (25) => parity=1
+prtyw (25) => parity=1
+prtyd (26) => parity=0
+prtyw (26) => parity=0
+prtyd (27) => parity=1
+prtyw (27) => parity=1
+prtyd (28) => parity=0
+prtyw (28) => parity=0
+prtyd (29) => parity=1
+prtyw (29) => parity=1
+prtyd (2a) => parity=0
+prtyw (2a) => parity=0
+prtyd (2b) => parity=1
+prtyw (2b) => parity=1
+prtyd (2c) => parity=0
+prtyw (2c) => parity=0
+prtyd (2d) => parity=1
+prtyw (2d) => parity=1
+prtyd (2e) => parity=0
+prtyw (2e) => parity=0
+prtyd (2f) => parity=1
+prtyw (2f) => parity=1
+prtyd (30) => parity=0
+prtyw (30) => parity=0
+prtyd (31) => parity=1
+prtyw (31) => parity=1