arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1

Add ICC_PPI_ENABLER<n>_EL1 registers sysreg description.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-6-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7f096efee4e7decf7f8b9cd3762d67ff3a3ad28e..728223df482d6fa5178c7f3f1c04a230a853ddc7 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3113,6 +3113,81 @@ Field    1       Enabled
 Field  0       F
 EndSysreg
 
+SysregFields   ICC_PPI_ENABLERx_EL1
+Field  63      EN63
+Field  62      EN62
+Field  61      EN61
+Field  60      EN60
+Field  59      EN59
+Field  58      EN58
+Field  57      EN57
+Field  56      EN56
+Field  55      EN55
+Field  54      EN54
+Field  53      EN53
+Field  52      EN52
+Field  51      EN51
+Field  50      EN50
+Field  49      EN49
+Field  48      EN48
+Field  47      EN47
+Field  46      EN46
+Field  45      EN45
+Field  44      EN44
+Field  43      EN43
+Field  42      EN42
+Field  41      EN41
+Field  40      EN40
+Field  39      EN39
+Field  38      EN38
+Field  37      EN37
+Field  36      EN36
+Field  35      EN35
+Field  34      EN34
+Field  33      EN33
+Field  32      EN32
+Field  31      EN31
+Field  30      EN30
+Field  29      EN29
+Field  28      EN28
+Field  27      EN27
+Field  26      EN26
+Field  25      EN25
+Field  24      EN24
+Field  23      EN23
+Field  22      EN22
+Field  21      EN21
+Field  20      EN20
+Field  19      EN19
+Field  18      EN18
+Field  17      EN17
+Field  16      EN16
+Field  15      EN15
+Field  14      EN14
+Field  13      EN13
+Field  12      EN12
+Field  11      EN11
+Field  10      EN10
+Field  9       EN9
+Field  8       EN8
+Field  7       EN7
+Field  6       EN6
+Field  5       EN5
+Field  4       EN4
+Field  3       EN3
+Field  2       EN2
+Field  1       EN1
+Field  0       EN0
+EndSysregFields
+
+Sysreg ICC_PPI_ENABLER0_EL1    3       0       12      10      6
+Fields ICC_PPI_ENABLERx_EL1
+EndSysreg
+
+Sysreg ICC_PPI_ENABLER1_EL1    3       0       12      10      7
+Fields ICC_PPI_ENABLERx_EL1
+EndSysreg
+
 SysregFields   ICC_PPI_PRIORITYRx_EL1
 Res0   63:61
 Field  60:56   Priority7