PCI: imx6: Add LUT configuration for MSI/IOMMU in Endpoint mode

Add LUT entry for MSI/IOMMU in Endpoint mode by calling
imx_pcie_add_lut_by_rid() helper function. Since only one physical function
is supported in the Endpoint mode for now, '0' is passed as the Device ID.
This sets up a single LUT entry required for MSI/IOMMU.

The Endpoint function can operate without LUT configuration if neither
IOMMU nor MSI is used by the platform. This LUT configuration is used for
the EP doorbell feature by allowing the Root Complex to trigger the
doorbell on the Endpoint with the help of the Endpoint MSI controller.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
[mani: reworded the comments & commit message and dropped tested-by tag]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250710-ep-msi-v21-2-57683fc7fb25@nxp.com

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 1f479da88fc85aa8aefe743e3fa9063bff77b568..eefe922d533bf8e39810c30a20c7a6287b8badbb 100644 (file)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1063,7 +1063,10 @@ static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid)
        data1 |= IMX95_PE0_LUT_VLD;
        regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1);
 
-       data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */
+       if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
+               data2 = 0x7; /* In the EP mode, only 'Device ID' is required */
+       else
+               data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */
        data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, rid);
        regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2);
 
@@ -1769,6 +1772,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
                ret = imx_add_pcie_ep(imx_pcie, pdev);
                if (ret < 0)
                        return ret;
+
+               /*
+                * FIXME: Only single Device (EPF) is supported due to the
+                * Endpoint framework limitation.
+                */
+               imx_pcie_add_lut_by_rid(imx_pcie, 0);
        } else {
                pci->pp.use_atu_msg = true;
                ret = dw_pcie_host_init(&pci->pp);