-From: Christian Marangi <ansuelsmth@gmail.com>
-To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,
- linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org
-Cc: Benjamin Larsson <benjamin.larsson@genexis.eu>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- Lorenzo Bianconi <lorenzo@kernel.org>,
- Christian Marangi <ansuelsmth@gmail.com>
-Subject: [PATCH v13] pwm: airoha: Add support for EN7581 SoC
-Date: Sat, 10 May 2025 00:36:52 +0200
-Message-ID: <20250509223653.8800-1-ansuelsmth@gmail.com>
-X-Mailer: git-send-email 2.48.1
-Precedence: bulk
-X-Mailing-List: linux-pwm@vger.kernel.org
-List-Id: <linux-pwm.vger.kernel.org>
-List-Subscribe: <mailto:linux-pwm+subscribe@vger.kernel.org>
-List-Unsubscribe: <mailto:linux-pwm+unsubscribe@vger.kernel.org>
-MIME-Version: 1.0
-
+From 61d7c2f94d391594de08d8a52a7c2630d2f3d263 Mon Sep 17 00:00:00 2001
From: Benjamin Larsson <benjamin.larsson@genexis.eu>
+Date: Mon, 13 Oct 2025 12:34:03 +0200
+Subject: [PATCH] pwm: airoha: Add support for EN7581 SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
Introduce driver for PWM module available on EN7581 SoC.
+Limitations:
+- Only 8 concurrent waveform generators are available for 8 combinations of
+ duty_cycle and period. Waveform generators are shared between 16 GPIO
+ pins and 17 SIPO GPIO pins.
+- Supports only normal polarity.
+- On configuration the currently running period is completed.
+- Minimum supported period is 4 ms
+- Maximum supported period is 1s
+
Signed-off-by: Benjamin Larsson <benjamin.larsson@genexis.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://patch.msgid.link/20251013103408.14724-1-ansuelsmth@gmail.com
+Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
---
-Changes v13:
-- Reorder include
-- Split ticks_from_ns function
-- Add additional comments for shift register chip clock
-- Address suggested minor optimization (Uwe)
-
-Changes v12:
-- Make shift function more readable
-- Use unsigned int where possible
-- Better comment some SIPO strangeness
-- Move SIPO init after flash map config
-- Retrun real values in get_state instead of the
- one saved in bucket
-- Improve period_ns parsing so we can better share generators
-
-Changes v11:
-- Fix wrong calculation of period and duty
-- Use AIROHA_PWM prefix for each define
-- Drop set/get special define in favour of BITS and GENMASK
-- Correctly use dev_err_probe
-- Init bucket with initial values
-- Rework define to make use of FIELD_PREP and FIELD_GET
-
-Changes in v10:
-- repost just patch 6/6 (pwm driver) since patches {1/6-5/6} have been
- already applied in linux-pinctrl tree
-- pwm: introduce AIROHA_PWM_FIELD_GET and AIROHA_PWM_FIELD_SET macros to
- get/set field with non-const mask
-- pwm: simplify airoha_pwm_get_generator() to report unused generator
- and remove double lookup
-- pwm: remove device_node pointer in airoha_pwm struct since this is
- write-only field
-- pwm: cosmetics
-- Link to v9: https://lore.kernel.org/r/20241023-en7581-pinctrl-v9-0-afb0cbcab0ec@kernel.org
-
-Changes in v9:
-- pwm: remove unused properties
-- Link to v8: https://lore.kernel.org/r/20241018-en7581-pinctrl-v8-0-b676b966a1d1@kernel.org
-
-Changes in v8:
-- pwm: add missing properties documentation
-- Link to v7: https://lore.kernel.org/r/20241016-en7581-pinctrl-v7-0-4ff611f263a7@kernel.org
-
-Changes in v7:
-- pinctrl: cosmetics
-- pinctrl: fix compilation warning
-- Link to v6: https://lore.kernel.org/r/20241013-en7581-pinctrl-v6-0-2048e2d099c2@kernel.org
-
-Changes in v6:
-- pwm: rely on regmap APIs
-- pwm: introduce compatible string
-- pinctrl: introduce compatible string
-- remove airoha-mfd driver
-- add airoha,en7581-pinctrl binding
-- add airoha,en7581-pwm binding
-- update airoha,en7581-gpio-sysctl binding
-- Link to v5: https://lore.kernel.org/r/20241001-en7581-pinctrl-v5-0-dc1ce542b6c6@kernel.org
-
-Changes in v5:
-- use spin_lock in airoha_pinctrl_rmw instead of a mutex since it can run
- in interrupt context
-- remove unused includes in pinctrl driver
-- since the irq_chip is immutable, allocate the gpio_irq_chip struct
- statically in pinctrl driver
-- rely on regmap APIs in pinctrl driver but keep the spin_lock local to the
- driver
-- rely on guard/guard_scope APIs in pinctrl driver
-- improve naming convention pinctrl driver
-- introduce airoha_pinconf_set_pin_value utility routine
-- Link to v4: https://lore.kernel.org/r/20240911-en7581-pinctrl-v4-0-60ac93d760bb@kernel.org
-
-Changes in v4:
-- add 'Limitation' description in pwm driver
-- fix comments in pwm driver
-- rely on mfd->base __iomem pointer in pwm driver, modify register
- offsets according to it and get rid of sgpio_cfg, flash_cfg and
- cycle_cfg pointers
-- simplify register utility routines in pwm driver
-- use 'generator' instead of 'waveform' suffix for pwm routines
-- fix possible overflow calculating duty cycle in pwm driver
-- do not modify pwm state in free callback in pwm driver
-- cap the maximum period in pwm driver
-- do not allow inverse polarity in pwm driver
-- do not set of_xlate callback in the pwm driver and allow the stack to
- do it
-- fix MAINTAINERS file for airoha pinctrl driver
-- fix undefined reference to __ffsdi2 in pinctrl driver
-- simplify airoha,en7581-gpio-sysctl.yam binding
-- Link to v3: https://lore.kernel.org/r/20240831-en7581-pinctrl-v3-0-98eebfb4da66@kernel.org
-
-Changes in v3:
-- introduce airoha-mfd driver
-- add pwm driver to the same series
-- model pinctrl and pwm drivers as childs of a parent mfd driver.
-- access chip-scu memory region in pinctrl driver via syscon
-- introduce a single airoha,en7581-gpio-sysctl.yaml binding and get rid
- of dedicated bindings for pinctrl and pwm
-- add airoha,en7581-chip-scu.yaml binding do the series
-- Link to v2: https://lore.kernel.org/r/20240822-en7581-pinctrl-v2-0-ba1559173a7f@kernel.org
-
-Changes in v2:
-- Fix compilation errors
-- Collapse some register mappings for gpio and irq controllers
-- update dt-bindings according to new register mapping
-- fix some dt-bindings errors
-- Link to v1: https://lore.kernel.org/all/cover.1723392444.git.lorenzo@kernel.org/
-
- drivers/pwm/Kconfig | 11 +
+ drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
- drivers/pwm/pwm-airoha.c | 536 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 548 insertions(+)
+ drivers/pwm/pwm-airoha.c | 622 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 633 insertions(+)
create mode 100644 drivers/pwm/pwm-airoha.c
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
-@@ -54,6 +54,17 @@ config PWM_ADP5585
+@@ -54,6 +54,16 @@ config PWM_ADP5585
This option enables support for the PWM function found in the Analog
Devices ADP5585.
+config PWM_AIROHA
+ tristate "Airoha PWM support"
+ depends on ARCH_AIROHA || COMPILE_TEST
-+ depends on OF
+ select REGMAP_MMIO
+ help
+ Generic PWM framework driver for Airoha SoC.
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
--- /dev/null
+++ b/drivers/pwm/pwm-airoha.c
-@@ -0,0 +1,536 @@
+@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Markus Gothe <markus.gothe@genexis.eu>
++ * Copyright 2025 Christian Marangi <ansuelsmth@gmail.com>
+ *
+ * Limitations:
+ * - Only 8 concurrent waveform generators are available for 8 combinations of
+ * pins and 17 SIPO GPIO pins.
+ * - Supports only normal polarity.
+ * - On configuration the currently running period is completed.
-+ * - Minimum supported period is 4ms
++ * - Minimum supported period is 4 ms
+ * - Maximum supported period is 1s
+ */
+
++#include <linux/array_size.h>
+#include <linux/bitfield.h>
-+#include <linux/bitops.h>
++#include <linux/bitmap.h>
+#include <linux/err.h>
-+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/math64.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
-+#include <linux/of.h>
++#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
++#include <linux/types.h>
+
+#define AIROHA_PWM_REG_SGPIO_LED_DATA 0x0024
+#define AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG BIT(31)
+
+#define AIROHA_PWM_REG_SGPIO_CLK_DIVR 0x0028
+#define AIROHA_PWM_SGPIO_CLK_DIVR GENMASK(1, 0)
-+#define AIROHA_PWM_SGPIO_CLK_DIVR_32 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x3)
-+#define AIROHA_PWM_SGPIO_CLK_DIVR_16 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x2)
-+#define AIROHA_PWM_SGPIO_CLK_DIVR_8 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x1)
-+#define AIROHA_PWM_SGPIO_CLK_DIVR_4 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x0)
++#define AIROHA_PWM_SGPIO_CLK_DIVR_32 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 3)
++#define AIROHA_PWM_SGPIO_CLK_DIVR_16 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 2)
++#define AIROHA_PWM_SGPIO_CLK_DIVR_8 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 1)
++#define AIROHA_PWM_SGPIO_CLK_DIVR_4 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0)
+
+#define AIROHA_PWM_REG_SGPIO_CLK_DLY 0x002c
+
+
+/* GPIO/SIPO flash map handles 8 pins in one register */
+#define AIROHA_PWM_PINS_PER_FLASH_MAP 8
-+/* Cycle cfg handles 4 generators in one register */
++/* Cycle(Period) registers handles 4 generators in one 32-bit register */
+#define AIROHA_PWM_BUCKET_PER_CYCLE_CFG 4
-+/* Flash producer handles 2 generators in one register */
++/* Flash(Duty) producer handles 2 generators in one 32-bit register */
+#define AIROHA_PWM_BUCKET_PER_FLASH_PROD 2
+
+#define AIROHA_PWM_NUM_BUCKETS 8
+#define AIROHA_PWM_MAX_CHANNELS (AIROHA_PWM_NUM_GPIO + AIROHA_PWM_NUM_SIPO)
+
+struct airoha_pwm_bucket {
-+ /* Bitmask of PWM channels using this bucket */
-+ u64 used;
-+ u64 period_ns;
-+ u64 duty_ns;
++ /* Concurrent access protected by PWM core */
++ int used;
++ u32 period_ticks;
++ u32 duty_ticks;
+};
+
+struct airoha_pwm {
+ struct regmap *regmap;
+
-+ u64 initialized;
++ DECLARE_BITMAP(initialized, AIROHA_PWM_MAX_CHANNELS);
+
+ struct airoha_pwm_bucket buckets[AIROHA_PWM_NUM_BUCKETS];
+
+ }
+}
+
-+static u32 airoha_pwm_get_period_ticks_from_ns(u64 period_ns)
++static u32 airoha_pwm_get_period_ticks_from_ns(u32 period_ns)
+{
-+ return div_u64(period_ns, AIROHA_PWM_PERIOD_TICK_NS);
++ return period_ns / AIROHA_PWM_PERIOD_TICK_NS;
+}
+
-+static u32 airoha_pwm_get_duty_ticks_from_ns(u64 period_ns, u64 duty_ns)
++static u32 airoha_pwm_get_duty_ticks_from_ns(u32 period_ns, u32 duty_ns)
+{
-+ return mul_u64_u64_div_u64(duty_ns, AIROHA_PWM_DUTY_FULL,
-+ period_ns);
++ return mul_u64_u32_div(duty_ns, AIROHA_PWM_DUTY_FULL, period_ns);
+}
+
-+static void airoha_pwm_get_bucket(struct airoha_pwm *pc, int bucket,
-+ u64 *period_ns, u64 *duty_ns)
++static u32 airoha_pwm_get_period_ns_from_ticks(u32 period_tick)
+{
++ return period_tick * AIROHA_PWM_PERIOD_TICK_NS;
++}
++
++static u32 airoha_pwm_get_duty_ns_from_ticks(u32 period_tick, u32 duty_tick)
++{
++ u32 period_ns = period_tick * AIROHA_PWM_PERIOD_TICK_NS;
++
++ /*
++ * Overflow can't occur in multiplication as duty_tick is just 8 bit
++ * and period_ns is clamped to AIROHA_PWM_PERIOD_MAX_NS and fit in a
++ * u64.
++ */
++ return DIV_U64_ROUND_UP(duty_tick * period_ns, AIROHA_PWM_DUTY_FULL);
++}
++
++static int airoha_pwm_get_bucket(struct airoha_pwm *pc, int bucket,
++ u64 *period_ns, u64 *duty_ns)
++{
++ struct regmap *map = pc->regmap;
+ u32 period_tick, duty_tick;
+ unsigned int offset;
+ u32 shift, val;
++ int ret;
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
+
-+ regmap_read(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), &val);
++ ret = regmap_read(map, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), &val);
++ if (ret)
++ return ret;
+
+ period_tick = FIELD_GET(AIROHA_PWM_WAVE_GEN_CYCLE, val >> shift);
-+ *period_ns = period_tick * AIROHA_PWM_PERIOD_TICK_NS;
++ *period_ns = airoha_pwm_get_period_ns_from_ticks(period_tick);
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
+
-+ regmap_read(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
-+ &val);
++ ret = regmap_read(map, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
++ &val);
++ if (ret)
++ return ret;
+
+ duty_tick = FIELD_GET(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, val >> shift);
-+ /*
-+ * Overflow can't occur in multiplication as duty_tick is just 8 bit
-+ * and period_ns is clamped to AIROHA_PWM_PERIOD_MAX_NS and fit in a
-+ * u64.
-+ */
-+ *duty_ns = DIV_U64_ROUND_UP(duty_tick * *period_ns, AIROHA_PWM_DUTY_FULL);
++ *duty_ns = airoha_pwm_get_duty_ns_from_ticks(period_tick, duty_tick);
++
++ return 0;
+}
+
-+static int airoha_pwm_get_generator(struct airoha_pwm *pc, u64 duty_ns,
-+ u64 period_ns)
++static int airoha_pwm_get_generator(struct airoha_pwm *pc, u32 duty_ticks,
++ u32 period_ticks)
+{
-+ int i, best = -ENOENT, unused = -ENOENT;
++ int best = -ENOENT, unused = -ENOENT;
++ u32 duty_ns, best_duty_ns = 0;
++ u32 best_period_ticks = 0;
++ unsigned int i;
++
++ duty_ns = airoha_pwm_get_duty_ns_from_ticks(period_ticks, duty_ticks);
+
+ for (i = 0; i < ARRAY_SIZE(pc->buckets); i++) {
+ struct airoha_pwm_bucket *bucket = &pc->buckets[i];
-+ u32 duty_ticks, duty_ticks_bucket;
++ u32 bucket_period_ticks = bucket->period_ticks;
++ u32 bucket_duty_ticks = bucket->duty_ticks;
+
+ /* If found, save an unused bucket to return it later */
-+ if (!bucket->used && unused == -ENOENT) {
++ if (!bucket->used) {
+ unused = i;
+ continue;
+ }
+
-+ if (duty_ns == bucket->duty_ns) {
-+ /* We found a matching bucket */
-+ if (period_ns == bucket->period_ns)
-+ return i;
-+
-+ /*
-+ * Save a bucket for later that is not bigger than the
-+ * requested period_ns (to be used if we don't have
-+ * any unused bucket)
-+ */
-+ if (bucket->period_ns <= period_ns)
-+ best = i;
-+ }
++ /* We found a matching bucket, exit early */
++ if (duty_ticks == bucket_duty_ticks &&
++ period_ticks == bucket_period_ticks)
++ return i;
+
+ /*
+ * Unlike duty cycle zero, which can be handled by
+ * disabling PWM, a generator is needed for full duty
+ * cycle but it can be reused regardless of period
+ */
-+ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
-+ duty_ticks_bucket = airoha_pwm_get_duty_ticks_from_ns(bucket->period_ns,
-+ bucket->duty_ns);
+ if (duty_ticks == AIROHA_PWM_DUTY_FULL &&
-+ duty_ticks_bucket == AIROHA_PWM_DUTY_FULL)
++ bucket_duty_ticks == AIROHA_PWM_DUTY_FULL)
+ return i;
++
++ /*
++ * With an unused bucket available, skip searching for
++ * a bucket to recycle (closer to the requested period/duty)
++ */
++ if (unused >= 0)
++ continue;
++
++ /* Ignore bucket with invalid period */
++ if (bucket_period_ticks > period_ticks)
++ continue;
++
++ /*
++ * Search for a bucket closer to the requested period
++ * that has the maximal possible period that isn't bigger
++ * than the requested period. For that period pick the maximal
++ * duty cycle that isn't bigger than the requested duty_cycle.
++ */
++ if (bucket_period_ticks >= best_period_ticks) {
++ u32 bucket_duty_ns = airoha_pwm_get_duty_ns_from_ticks(bucket_period_ticks,
++ bucket_duty_ticks);
++
++ /* Skip bucket that goes over the requested duty */
++ if (bucket_duty_ns > duty_ns)
++ continue;
++
++ if (bucket_duty_ns > best_duty_ns) {
++ best_period_ticks = bucket_period_ticks;
++ best_duty_ns = bucket_duty_ns;
++ best = i;
++ }
++ }
+ }
+
-+ /* With no unused bucket, return the best one found (if ever) */
-+ return unused == -ENOENT ? best : unused;
++ /* Return an unused bucket or the best one found (if ever) */
++ return unused >= 0 ? unused : best;
+}
+
+static void airoha_pwm_release_bucket_config(struct airoha_pwm *pc,
+ int bucket;
+
+ /* Nothing to clear, PWM channel never used */
-+ if (!(pc->initialized & BIT_ULL(hwpwm)))
++ if (!test_bit(hwpwm, pc->initialized))
+ return;
+
+ bucket = pc->channel_bucket[hwpwm];
-+ pc->buckets[bucket].used &= ~BIT_ULL(hwpwm);
++ pc->buckets[bucket].used--;
++}
++
++static int airoha_pwm_apply_bucket_config(struct airoha_pwm *pc, unsigned int bucket,
++ u32 duty_ticks, u32 period_ticks)
++{
++ u32 mask, shift, val;
++ u32 offset;
++ int ret;
++
++ offset = bucket / AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
++ shift = bucket % AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
++ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
++
++ /* Configure frequency divisor */
++ mask = AIROHA_PWM_WAVE_GEN_CYCLE << shift;
++ val = FIELD_PREP(AIROHA_PWM_WAVE_GEN_CYCLE, period_ticks) << shift;
++ ret = regmap_update_bits(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset),
++ mask, val);
++ if (ret)
++ return ret;
++
++ offset = bucket / AIROHA_PWM_BUCKET_PER_FLASH_PROD;
++ shift = bucket % AIROHA_PWM_BUCKET_PER_FLASH_PROD;
++ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
++
++ /* Configure duty cycle */
++ mask = AIROHA_PWM_GPIO_FLASH_PRD_HIGH << shift;
++ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, duty_ticks) << shift;
++ ret = regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
++ mask, val);
++ if (ret)
++ return ret;
++
++ mask = AIROHA_PWM_GPIO_FLASH_PRD_LOW << shift;
++ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_LOW,
++ AIROHA_PWM_DUTY_FULL - duty_ticks) << shift;
++ return regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
++ mask, val);
+}
+
+static int airoha_pwm_consume_generator(struct airoha_pwm *pc,
-+ u64 duty_ns, u64 period_ns,
++ u32 duty_ticks, u32 period_ticks,
+ unsigned int hwpwm)
+{
-+ int bucket;
++ bool config_bucket = false;
++ int bucket, ret;
+
+ /*
-+ * Search for a bucket that already satisfy duty and period
++ * Search for a bucket that already satisfies duty and period
+ * or an unused one.
+ * If not found, -ENOENT is returned.
+ */
-+ bucket = airoha_pwm_get_generator(pc, duty_ns, period_ns);
++ bucket = airoha_pwm_get_generator(pc, duty_ticks, period_ticks);
+ if (bucket < 0)
+ return bucket;
+
++ /* Release previous used bucket (if any) */
+ airoha_pwm_release_bucket_config(pc, hwpwm);
-+ pc->buckets[bucket].used |= BIT_ULL(hwpwm);
-+ pc->buckets[bucket].period_ns = period_ns;
-+ pc->buckets[bucket].duty_ns = duty_ns;
++
++ if (!pc->buckets[bucket].used)
++ config_bucket = true;
++ pc->buckets[bucket].used++;
++
++ if (config_bucket) {
++ pc->buckets[bucket].period_ticks = period_ticks;
++ pc->buckets[bucket].duty_ticks = duty_ticks;
++ ret = airoha_pwm_apply_bucket_config(pc, bucket,
++ duty_ticks,
++ period_ticks);
++ if (ret) {
++ pc->buckets[bucket].used--;
++ return ret;
++ }
++ }
+
+ return bucket;
+}
+static int airoha_pwm_sipo_init(struct airoha_pwm *pc)
+{
+ u32 val;
++ int ret;
+
-+ if (!(pc->initialized >> AIROHA_PWM_NUM_GPIO))
-+ return 0;
-+
-+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
-+ AIROHA_PWM_SERIAL_GPIO_MODE_74HC164);
++ ret = regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
++ AIROHA_PWM_SERIAL_GPIO_MODE_74HC164);
++ if (ret)
++ return ret;
+
+ /* Configure shift register chip clock timings, use 32x divisor */
-+ regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DIVR,
-+ AIROHA_PWM_SGPIO_CLK_DIVR_32);
++ ret = regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DIVR,
++ AIROHA_PWM_SGPIO_CLK_DIVR_32);
++ if (ret)
++ return ret;
+
+ /*
+ * Configure the shift register chip clock delay. This needs
+ * From documentation is specified that clock delay should not be
+ * greater than (AIROHA_PWM_REG_SGPIO_CLK_DIVR / 2) - 1.
+ */
-+ regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DLY, 0x0);
++ ret = regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DLY, 0);
++ if (ret)
++ return ret;
+
+ /*
+ * It is necessary to explicitly shift out all zeros after muxing
+ * mode because in PWM mode SIPO will not start shifting until
+ * it needs to output a non-zero value (bit 31 of led_data
+ * indicates shifting in progress and it must return to zero
-+ * before led_data can be written or PWM mode can be set)
++ * before led_data can be written or PWM mode can be set).
+ */
-+ if (regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
-+ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
-+ 10, 200 * USEC_PER_MSEC))
-+ return -ETIMEDOUT;
-+
-+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA,
-+ AIROHA_PWM_SGPIO_LED_DATA_DATA);
-+ if (regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
-+ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
-+ 10, 200 * USEC_PER_MSEC))
-+ return -ETIMEDOUT;
-+
-+ /* Set SIPO in PWM mode */
-+ regmap_set_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
-+ AIROHA_PWM_SERIAL_GPIO_FLASH_MODE);
-+
-+ return 0;
-+}
-+
-+static void airoha_pwm_calc_bucket_config(struct airoha_pwm *pc, int bucket,
-+ u64 duty_ns, u64 period_ns)
-+{
-+ u32 period_ticks, duty_ticks;
-+ u32 mask, shift, val;
-+ u64 offset;
-+
-+ period_ticks = airoha_pwm_get_period_ticks_from_ns(period_ns);
-+ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
-+
-+ offset = bucket;
-+ shift = do_div(offset, AIROHA_PWM_BUCKET_PER_CYCLE_CFG);
-+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
-+
-+ /* Configure frequency divisor */
-+ mask = AIROHA_PWM_WAVE_GEN_CYCLE << shift;
-+ val = FIELD_PREP(AIROHA_PWM_WAVE_GEN_CYCLE, period_ticks) << shift;
-+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), mask, val);
-+
-+ offset = bucket;
-+ shift = do_div(offset, AIROHA_PWM_BUCKET_PER_FLASH_PROD);
-+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
++ ret = regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
++ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
++ 10, 200 * USEC_PER_MSEC);
++ if (ret)
++ return ret;
+
-+ /* Configure duty cycle */
-+ mask = AIROHA_PWM_GPIO_FLASH_PRD_HIGH << shift;
-+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, duty_ticks) << shift;
-+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
-+ mask, val);
++ ret = regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA,
++ AIROHA_PWM_SGPIO_LED_DATA_DATA);
++ if (ret)
++ return ret;
++ ret = regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
++ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
++ 10, 200 * USEC_PER_MSEC);
++ if (ret)
++ return ret;
+
-+ mask = AIROHA_PWM_GPIO_FLASH_PRD_LOW << shift;
-+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_LOW,
-+ AIROHA_PWM_DUTY_FULL - duty_ticks) << shift;
-+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
-+ mask, val);
++ /* Set SIPO in PWM mode */
++ return regmap_set_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
++ AIROHA_PWM_SERIAL_GPIO_FLASH_MODE);
+}
+
-+static void airoha_pwm_config_flash_map(struct airoha_pwm *pc,
-+ unsigned int hwpwm, int index)
++static int airoha_pwm_config_flash_map(struct airoha_pwm *pc,
++ unsigned int hwpwm, int index)
+{
+ unsigned int addr;
+ u32 shift;
++ int ret;
+
+ airoha_pwm_get_flash_map_addr_and_shift(hwpwm, &addr, &shift);
+
-+ /* index -1 means disable PWM channel */
++ /* negative index means disable PWM channel */
+ if (index < 0) {
+ /*
+ * If we need to disable the PWM, we just put low the
+ * GPIO. No need to setup buckets.
+ */
-+ regmap_clear_bits(pc->regmap, addr,
-+ AIROHA_PWM_GPIO_FLASH_EN << shift);
-+ return;
++ return regmap_clear_bits(pc->regmap, addr,
++ AIROHA_PWM_GPIO_FLASH_EN << shift);
+ }
+
-+ regmap_update_bits(pc->regmap, addr,
-+ AIROHA_PWM_GPIO_FLASH_SET_ID << shift,
-+ FIELD_PREP(AIROHA_PWM_GPIO_FLASH_SET_ID, index) << shift);
-+ regmap_set_bits(pc->regmap, addr, AIROHA_PWM_GPIO_FLASH_EN << shift);
++ ret = regmap_update_bits(pc->regmap, addr,
++ AIROHA_PWM_GPIO_FLASH_SET_ID << shift,
++ FIELD_PREP(AIROHA_PWM_GPIO_FLASH_SET_ID, index) << shift);
++ if (ret)
++ return ret;
++
++ return regmap_set_bits(pc->regmap, addr, AIROHA_PWM_GPIO_FLASH_EN << shift);
+}
+
+static int airoha_pwm_config(struct airoha_pwm *pc, struct pwm_device *pwm,
-+ u64 duty_ns, u64 period_ns)
++ u32 period_ticks, u32 duty_ticks)
+{
+ unsigned int hwpwm = pwm->hwpwm;
-+ int bucket;
++ int bucket, ret;
+
-+ bucket = airoha_pwm_consume_generator(pc, duty_ns, period_ns,
++ bucket = airoha_pwm_consume_generator(pc, duty_ticks, period_ticks,
+ hwpwm);
+ if (bucket < 0)
-+ return -EBUSY;
++ return bucket;
+
-+ airoha_pwm_calc_bucket_config(pc, bucket, duty_ns, period_ns);
-+ airoha_pwm_config_flash_map(pc, hwpwm, bucket);
++ ret = airoha_pwm_config_flash_map(pc, hwpwm, bucket);
++ if (ret) {
++ pc->buckets[bucket].used--;
++ return ret;
++ }
+
-+ pc->initialized |= BIT_ULL(hwpwm);
++ __set_bit(hwpwm, pc->initialized);
+ pc->channel_bucket[hwpwm] = bucket;
+
+ /*
+ * of this chip is internal to the SoC that takes care of applying the
+ * values based on the flash map. To apply a new flash map, it's needed
+ * to trigger a refresh on the shift register chip.
-+ * If we are configuring a SIPO, always reinit the shift register chip
-+ * to make sure the correct flash map is applied.
-+ * We skip reconfiguring the shift register if we related hwpwm
++ * If a SIPO is getting configuring , always reinit the shift register
++ * chip to make sure the correct flash map is applied.
++ * Skip reconfiguring the shift register if the related hwpwm
+ * is disabled (as it doesn't need to be mapped).
+ */
-+ if (!(pc->initialized & BIT_ULL(hwpwm)) && hwpwm >= AIROHA_PWM_NUM_GPIO)
-+ airoha_pwm_sipo_init(pc);
++ if (hwpwm >= AIROHA_PWM_NUM_GPIO) {
++ ret = airoha_pwm_sipo_init(pc);
++ if (ret) {
++ airoha_pwm_release_bucket_config(pc, hwpwm);
++ return ret;
++ }
++ }
+
+ return 0;
+}
+ airoha_pwm_config_flash_map(pc, pwm->hwpwm, -1);
+ airoha_pwm_release_bucket_config(pc, pwm->hwpwm);
+
-+ pc->initialized &= ~BIT_ULL(pwm->hwpwm);
++ __clear_bit(pwm->hwpwm, pc->initialized);
+
+ /* If no SIPO is used, disable the shift register chip */
-+ if (!(pc->initialized >> AIROHA_PWM_NUM_GPIO))
++ if (!bitmap_read(pc->initialized,
++ AIROHA_PWM_NUM_GPIO, AIROHA_PWM_NUM_SIPO))
+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ AIROHA_PWM_SERIAL_GPIO_FLASH_MODE);
+}
+ const struct pwm_state *state)
+{
+ struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
-+ u64 duty_ns = state->duty_cycle;
-+ u64 period_ns = state->period;
-+
-+ /* Only normal polarity is supported */
-+ if (state->polarity == PWM_POLARITY_INVERSED)
-+ return -EINVAL;
++ u32 period_ticks, duty_ticks;
++ u32 period_ns, duty_ns;
+
+ if (!state->enabled) {
+ airoha_pwm_disable(pc, pwm);
+ return 0;
+ }
+
-+ /* Exit early if period is less than minimum supported */
-+ if (period_ns < AIROHA_PWM_PERIOD_TICK_NS)
++ /* Only normal polarity is supported */
++ if (state->polarity == PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
-+ /*
-+ * Period goes at 4ns step, normalize it to check if we can
-+ * share a generator.
-+ */
-+ period_ns = rounddown(period_ns, AIROHA_PWM_PERIOD_TICK_NS);
++ /* Exit early if period is less than minimum supported */
++ if (state->period < AIROHA_PWM_PERIOD_TICK_NS)
++ return -EINVAL;
+
+ /* Clamp period to MAX supported value */
-+ if (period_ns > AIROHA_PWM_PERIOD_MAX_NS) {
++ if (state->period > AIROHA_PWM_PERIOD_MAX_NS)
+ period_ns = AIROHA_PWM_PERIOD_MAX_NS;
++ else
++ period_ns = state->period;
+
-+ if (duty_ns > period_ns)
-+ duty_ns = period_ns;
-+ }
++ /* Validate duty to configured period */
++ if (state->duty_cycle > period_ns)
++ duty_ns = period_ns;
++ else
++ duty_ns = state->duty_cycle;
+
-+ return airoha_pwm_config(pc, pwm, duty_ns, period_ns);
++ /* Convert period ns to ticks */
++ period_ticks = airoha_pwm_get_period_ticks_from_ns(period_ns);
++ /* Convert period ticks to ns again for cosistent duty tick calculation */
++ period_ns = airoha_pwm_get_period_ns_from_ticks(period_ticks);
++ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
++
++ return airoha_pwm_config(pc, pwm, period_ticks, duty_ticks);
+}
+
+static int airoha_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ state->polarity = PWM_POLARITY_NORMAL;
+
+ bucket = FIELD_GET(AIROHA_PWM_GPIO_FLASH_SET_ID, val >> shift);
-+ airoha_pwm_get_bucket(pc, bucket, &state->period,
-+ &state->duty_cycle);
-+
-+ return 0;
++ return airoha_pwm_get_bucket(pc, bucket, &state->period,
++ &state->duty_cycle);
+}
+
+static const struct pwm_ops airoha_pwm_ops = {
+ chip->ops = &airoha_pwm_ops;
+ pc = pwmchip_get_drvdata(chip);
+
-+ pc->regmap = device_node_to_regmap(dev->parent->of_node);
++ pc->regmap = device_node_to_regmap(dev_of_node(dev->parent));
+ if (IS_ERR(pc->regmap))
+ return dev_err_probe(dev, PTR_ERR(pc->regmap), "Failed to get PWM regmap\n");
+
-+ ret = devm_pwmchip_add(&pdev->dev, chip);
++ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+
+static struct platform_driver airoha_pwm_driver = {
+ .driver = {
+ .name = "pwm-airoha",
++ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ .of_match_table = airoha_pwm_of_match,
+ },
+ .probe = airoha_pwm_probe,
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Airoha EN7581 PWM driver");
+MODULE_LICENSE("GPL");
projects / thirdparty / openwrt.git / commitdiff
