goto decode_success;
}
+ /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */
+ if (insn[0] == 0x0F && insn[1] == 0x5E) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+2, "divps", Iop_Div32Fx4 );
+ goto decode_success;
+ }
+
+ /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */
+ if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5E) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+3, "divss", Iop_Div32F0x4 );
+ goto decode_success;
+ }
+
+ /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */
+ if (insn[0] == 0x0F && insn[1] == 0x5F) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+2, "maxps", Iop_Max32Fx4 );
+ goto decode_success;
+ }
+
+ /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */
+ if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5F) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+3, "maxss", Iop_Max32F0x4 );
+ goto decode_success;
+ }
+
+ /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */
+ if (insn[0] == 0x0F && insn[1] == 0x5D) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+2, "minps", Iop_Min32Fx4 );
+ goto decode_success;
+ }
+
+ /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */
+ if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5D) {
+ vassert(sz == 4);
+ delta = dis_SSE_E_to_G( sorb, delta+3, "minss", Iop_Min32F0x4 );
+ goto decode_success;
+ }
//--
//-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
case Xsse_ADDF: return "add";
case Xsse_SUBF: return "sub";
case Xsse_MULF: return "mul";
+ case Xsse_DIVF: return "div";
+ case Xsse_MAXF: return "max";
+ case Xsse_MINF: return "min";
case Xsse_CMPEQF: return "cmpFeq";
case Xsse_CMPLTF: return "cmpFlt";
case Xsse_CMPLEF: return "cmpFle";
*p++ = 0x0F;
switch (i->Xin.Sse32Fx4.op) {
case Xsse_ADDF: *p++ = 0x58; break;
+ case Xsse_DIVF: *p++ = 0x5E; break;
+ case Xsse_MAXF: *p++ = 0x5F; break;
+ case Xsse_MINF: *p++ = 0x5D; break;
case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break;
case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break;
case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break;
*p++ = 0x0F;
switch (i->Xin.Sse32FLo.op) {
case Xsse_ADDF: *p++ = 0x58; break;
+ case Xsse_DIVF: *p++ = 0x5E; break;
+ case Xsse_MAXF: *p++ = 0x5F; break;
+ case Xsse_MINF: *p++ = 0x5D; break;
case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break;
case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break;
case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break;
enum {
Xsse_INVALID,
Xsse_MOV, Xsse_AND, Xsse_OR, Xsse_XOR, Xsse_ANDN,
- Xsse_ADDF, Xsse_SUBF, Xsse_MULF,
+ Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF,
+ Xsse_MAXF, Xsse_MINF,
Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF
}
X86SseOp;
case Iop_CmpLT32Fx4: op = Xsse_CMPLTF; goto do_32Fx4;
case Iop_CmpLE32Fx4: op = Xsse_CMPLEF; goto do_32Fx4;
case Iop_Add32Fx4: op = Xsse_ADDF; goto do_32Fx4;
+ case Iop_Div32Fx4: op = Xsse_DIVF; goto do_32Fx4;
+ case Iop_Max32Fx4: op = Xsse_MAXF; goto do_32Fx4;
+ case Iop_Min32Fx4: op = Xsse_MINF; goto do_32Fx4;
do_32Fx4:
{
HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
case Iop_CmpLT32F0x4: op = Xsse_CMPLTF; goto do_32F0x4;
case Iop_CmpLE32F0x4: op = Xsse_CMPLEF; goto do_32F0x4;
case Iop_Add32F0x4: op = Xsse_ADDF; goto do_32F0x4;
+ case Iop_Div32F0x4: op = Xsse_DIVF; goto do_32F0x4;
+ case Iop_Max32F0x4: op = Xsse_MAXF; goto do_32F0x4;
+ case Iop_Min32F0x4: op = Xsse_MINF; goto do_32F0x4;
do_32F0x4: {
HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
case Iop_Add32Fx4: vex_printf("Add32Fx4"); return;
case Iop_Add32F0x4: vex_printf("Add32F0x4"); return;
+ case Iop_Div32Fx4: vex_printf("Div32Fx4"); return;
+ case Iop_Div32F0x4: vex_printf("Div32F0x4"); return;
+
+ case Iop_Max32Fx4: vex_printf("Max32Fx4"); return;
+ case Iop_Max32F0x4: vex_printf("Max32F0x4"); return;
+
+ case Iop_Min32Fx4: vex_printf("Min32Fx4"); return;
+ case Iop_Min32F0x4: vex_printf("Min32F0x4"); return;
+
case Iop_CmpEQ32Fx4: vex_printf("CmpEQ32Fx4"); return;
case Iop_CmpLT32Fx4: vex_printf("CmpLT32Fx4"); return;
case Iop_CmpLE32Fx4: vex_printf("CmpLE32Fx4"); return;
case Iop_CmpEQ32F0x4: case Iop_CmpLT32F0x4:
case Iop_CmpLE32F0x4: case Iop_CmpUN32F0x4:
case Iop_Add32Fx4: case Iop_Add32F0x4:
+ case Iop_Div32Fx4: case Iop_Div32F0x4:
+ case Iop_Max32Fx4: case Iop_Max32F0x4:
+ case Iop_Min32Fx4: case Iop_Min32F0x4:
case Iop_And128: case Iop_Or128: case Iop_Xor128:
BINARY(Ity_V128, Ity_V128,Ity_V128);