net: mdio: mux-meson-gxl: set reversed bit when using internal phy

[ Upstream commit b23285e93bef729e67519a5209d5b7fde3b4af50 ]

This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.

Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.
If bit is set once, it will work until the IP is powered down or reset.

The vendor SDK sets this bit along with the PHY_ID bits.

Signed-off-by: Da Xue <da@libre.computer>
Fixes: 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support")
Link: https://patch.msgid.link/20250425192009.1439508-1-da@libre.computer
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c b/drivers/net/mdio/mdio-mux-meson-gxl.c
index 76188575ca1fcf29b4b76942540cabdf9a48f82e..19153d44800a942d964b26ff2e5a38625575cd8b 100644 (file)
--- a/drivers/net/mdio/mdio-mux-meson-gxl.c
+++ b/drivers/net/mdio/mdio-mux-meson-gxl.c
@@ -17,6 +17,7 @@
 #define  REG2_LEDACT           GENMASK(23, 22)
 #define  REG2_LEDLINK          GENMASK(25, 24)
 #define  REG2_DIV4SEL          BIT(27)
+#define  REG2_REVERSED         BIT(28)
 #define  REG2_ADCBYPASS                BIT(30)
 #define  REG2_CLKINSEL         BIT(31)
 #define ETH_REG3               0x4
@@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct gxl_mdio_mux *priv)
         * The only constraint is that it must match the one in
         * drivers/net/phy/meson-gxl.c to properly match the PHY.
         */
-       writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
+       writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
               priv->regs + ETH_REG2);
 
        /* Enable the internal phy */