LoongArch: KVM: Fix HW timer interrupt lost when inject interrupt by software

With passthrough HW timer, timer interrupt is injected by HW. When
inject emulated CPU interrupt by software such SIP0/SIP1/IPI, HW timer
interrupt may be lost.

Here check whether there is timer tick value inversion before and after
injecting emulated CPU interrupt by software, timer enabling by reading
timer cfg register is skipped. If the timer tick value is detected with
changing, then timer should be enabled. And inject a timer interrupt by
software if there is.

Cc: <stable@vger.kernel.org>
Fixes: f45ad5b8aa93 ("LoongArch: KVM: Implement vcpu interrupt operations").
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c
index 53dac8ab8fb1306bcfbbf094d2a97af1c4719804..a18c60dffbbaea15321f2323a0b03c1d208e72d3 100644 (file)
--- a/arch/loongarch/kvm/interrupt.c
+++ b/arch/loongarch/kvm/interrupt.c
@@ -28,6 +28,7 @@ static unsigned int priority_to_irq[EXCCODE_INT_NUM] = {
 static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
 {
        unsigned int irq = 0;
+       unsigned long old, new;
 
        clear_bit(priority, &vcpu->arch.irq_pending);
        if (priority < EXCCODE_INT_NUM)
@@ -43,7 +44,13 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
        case INT_IPI:
        case INT_SWI0:
        case INT_SWI1:
+               old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
                set_gcsr_estat(irq);
+               new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
+
+               /* Inject TI if TVAL inverted */
+               if (new > old)
+                       set_gcsr_estat(CPU_TIMER);
                break;
 
        case INT_HWI0 ... INT_HWI7:
@@ -60,6 +67,7 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
 static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority)
 {
        unsigned int irq = 0;
+       unsigned long old, new;
 
        clear_bit(priority, &vcpu->arch.irq_clear);
        if (priority < EXCCODE_INT_NUM)
@@ -74,7 +82,13 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority)
        case INT_IPI:
        case INT_SWI0:
        case INT_SWI1:
+               old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
                clear_gcsr_estat(irq);
+               new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL);
+
+               /* Inject TI if TVAL inverted */
+               if (new > old)
+                       set_gcsr_estat(CPU_TIMER);
                break;
 
        case INT_HWI0 ... INT_HWI7: