arm64: dts: qcom: sc7180: Fix the LLCC base register size

[ Upstream commit efe788361f72914017515223414d3f20abe4b403 ]

There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 31b9217bb5bfe0f2499abd9de4ee46510e91a135..cfeeddcea7887bfb0d944f911556cd76299eaacf 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2193,7 +2193,7 @@
 
                system-cache-controller@9200000 {
                        compatible = "qcom,sc7180-llcc";
-                       reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
+                       reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
                        reg-names = "llcc_base", "llcc_broadcast_base";
                        interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
                };