]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
s390: Fix up *cmp_and_trap_unsigned_int<mode> constraints [PR104775]
authorJakub Jelinek <jakub@redhat.com>
Mon, 7 Mar 2022 10:14:04 +0000 (11:14 +0100)
committerJakub Jelinek <jakub@redhat.com>
Mon, 7 Mar 2022 10:14:04 +0000 (11:14 +0100)
The following testcase fails to assemble due to clgte %r6,0(%r1,%r10)
insn not being accepted by assembler.
My rough understanding is that in the RSY-b insn format the spot
in other formats used for index registers is used instead for M3 what
kind of comparison it is, so this patch follows what other similar
instructions use for constraint (i.e. one without index register).

2022-03-07  Jakub Jelinek  <jakub@redhat.com>

PR target/104775
* config/s390/s390.md (*cmp_and_trap_unsigned_int<mode>): Use
S constraint instead of T in the last alternative.

* gcc.target/s390/pr104775.c: New test.

gcc/config/s390/s390.md
gcc/testsuite/gcc.target/s390/pr104775.c [new file with mode: 0644]

index 5eee8e86b423bc3cb778087bed8ecdda6d2479c3..d0f233e016b2b7e782152ed9f7a7ea0115b9f065 100644 (file)
 (define_insn "*cmp_and_trap_unsigned_int<mode>"
   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
               [(match_operand:GPR 1 "register_operand" "d,d,d")
-               (match_operand:GPR 2 "general_operand"  "d,D,T")])
+               (match_operand:GPR 2 "general_operand"  "d,D,S")])
            (const_int 0))]
   "TARGET_Z10"
   "@
diff --git a/gcc/testsuite/gcc.target/s390/pr104775.c b/gcc/testsuite/gcc.target/s390/pr104775.c
new file mode 100644 (file)
index 0000000..fd4258b
--- /dev/null
@@ -0,0 +1,14 @@
+/* PR target/104775 */
+/* { dg-do assemble { target s390_zEC12_hw } } */
+/* { dg-options "-O2 -march=zEC12" } */
+
+long a[64];
+void bar (void);
+
+void
+foo (int x, int y)
+{
+  if (x != a[y])
+    bar ();
+  __builtin_trap ();
+}