x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache

commit c21b90f77687075115d989e53a8ec5e2bb427ab1 upstream.

Make sure resources are not improperly shared in the op cache and
cause instruction corruption this way.

Signed-off-by: Prathyushi Nangia <prathyushi.nangia@amd.com>
Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 5b8268afc0358c89e0d83ef7ad9a3c6a98fcb740..b05866fd2b73fdbc3d6d4fd2a8372780d91fbabe 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -672,6 +672,7 @@
 /* Zen4 */
 #define MSR_ZEN4_BP_CFG                        0xc001102e
 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
+#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT    33
 
 /* Zen 2 */
 #define MSR_ZEN2_SPECTRAL_CHICKEN      0xc00110e3

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f5df16d77d5570571b6d8e339c452ae1c15971ff..df6dbeeca5565e27579b82dae6fa308c7e8415a8 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1146,6 +1146,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 {
        init_amd_zen_common();
        init_spectral_chicken(c);
+
+       if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
+               msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index f17ade084720d508e133ff115cf6c6ae7d65c008..f4110adf086c4deda5fe0772d6a9319e5aaaca1c 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -598,6 +598,9 @@
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT                   0xc000010e
 
+#define MSR_ZEN4_BP_CFG                        0xc001102e
+#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT    33
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF                        0xc00000e9