arm64: Disable GICv5 read/write/instruction traps

GICv5 trap configuration registers value is UNKNOWN at reset.

Initialize GICv5 EL2 trap configuration registers to prevent
trapping GICv5 instruction/register access upon entering the
kernel.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-15-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index ba5df0df02a467c800e262094b5c9e7f5911e760..54abcb13e51f4f36bf4cfaad786151e127bd23b4 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -165,6 +165,50 @@
 .Lskip_gicv3_\@:
 .endm
 
+/* GICv5 system register access */
+.macro __init_el2_gicv5
+       mrs_s   x0, SYS_ID_AA64PFR2_EL1
+       ubfx    x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4
+       cbz     x0, .Lskip_gicv5_\@
+
+       mov     x0, #(ICH_HFGITR_EL2_GICRCDNMIA         | \
+                     ICH_HFGITR_EL2_GICRCDIA           | \
+                     ICH_HFGITR_EL2_GICCDDI            | \
+                     ICH_HFGITR_EL2_GICCDEOI           | \
+                     ICH_HFGITR_EL2_GICCDHM            | \
+                     ICH_HFGITR_EL2_GICCDRCFG          | \
+                     ICH_HFGITR_EL2_GICCDPEND          | \
+                     ICH_HFGITR_EL2_GICCDAFF           | \
+                     ICH_HFGITR_EL2_GICCDPRI           | \
+                     ICH_HFGITR_EL2_GICCDDIS           | \
+                     ICH_HFGITR_EL2_GICCDEN)
+       msr_s   SYS_ICH_HFGITR_EL2, x0          // Disable instruction traps
+       mov_q   x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1        | \
+                    ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1      | \
+                    ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1          | \
+                    ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1        | \
+                    ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1            | \
+                    ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1             | \
+                    ICH_HFGRTR_EL2_ICC_ICSR_EL1                | \
+                    ICH_HFGRTR_EL2_ICC_PCR_EL1                 | \
+                    ICH_HFGRTR_EL2_ICC_HPPIR_EL1               | \
+                    ICH_HFGRTR_EL2_ICC_HAPR_EL1                | \
+                    ICH_HFGRTR_EL2_ICC_CR0_EL1                 | \
+                    ICH_HFGRTR_EL2_ICC_IDRn_EL1                | \
+                    ICH_HFGRTR_EL2_ICC_APR_EL1)
+       msr_s   SYS_ICH_HFGRTR_EL2, x0          // Disable reg read traps
+       mov_q   x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1        | \
+                    ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1      | \
+                    ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1          | \
+                    ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1        | \
+                    ICH_HFGWTR_EL2_ICC_ICSR_EL1                | \
+                    ICH_HFGWTR_EL2_ICC_PCR_EL1                 | \
+                    ICH_HFGWTR_EL2_ICC_CR0_EL1                 | \
+                    ICH_HFGWTR_EL2_ICC_APR_EL1)
+       msr_s   SYS_ICH_HFGWTR_EL2, x0          // Disable reg write traps
+.Lskip_gicv5_\@:
+.endm
+
 .macro __init_el2_hstr
        msr     hstr_el2, xzr                   // Disable CP15 traps to EL2
 .endm
@@ -314,6 +358,7 @@
        __init_el2_lor
        __init_el2_stage2
        __init_el2_gicv3
+       __init_el2_gicv5
        __init_el2_hstr
        __init_el2_nvhe_idregs
        __init_el2_cptr