]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT setting
authorTimur Kristóf <timur.kristof@gmail.com>
Mon, 19 Jan 2026 20:36:22 +0000 (21:36 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 21 Jan 2026 19:17:13 +0000 (14:17 -0500)
Use WREG32 to write mmCG_THERMAL_INT.
This is a direct access register.

Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

index 9bdcd4e2aeb2242b608e3233ac98a04e47436621..f7c2b1d206b6325fb2d24e2a45357dfbf72065f9 100644 (file)
@@ -7600,12 +7600,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
                case AMDGPU_IRQ_STATE_DISABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                case AMDGPU_IRQ_STATE_ENABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                default:
                        break;
@@ -7617,12 +7617,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
                case AMDGPU_IRQ_STATE_DISABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                case AMDGPU_IRQ_STATE_ENABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                default:
                        break;