ice: fix PHY timestamp extraction for ETH56G

[ Upstream commit 3214fae85e8336fe13e20cf78fc9b6a668bdedff ]

Fix incorrect PHY timestamp extraction for ETH56G.
It's better to use FIELD_PREP() than manual shift.

Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Przemyslaw Korba <przemyslaw.korba@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index ec8db830ac73ae12be88df20cb333854752a0713..3816e45b6ab44a35887aab1494cdc08ad0f88ce9 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -1495,7 +1495,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
         * lower 8 bits in the low register, and the upper 32 bits in the high
         * register.
         */
-       *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
+       *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) |
+                 FIELD_PREP(TS_PHY_LOW_M, lo);
 
        return 0;
 }

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 6cedc1a906afb6f68408ccc28a65e8ef2b88f88b..4c8b8457134427b9982d96e45c22ef469aaa3db1 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -663,9 +663,8 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
 #define TS_HIGH_M                      0xFF
 #define TS_HIGH_S                      32
 
-#define TS_PHY_LOW_M                   0xFF
-#define TS_PHY_HIGH_M                  0xFFFFFFFF
-#define TS_PHY_HIGH_S                  8
+#define TS_PHY_LOW_M                   GENMASK(7, 0)
+#define TS_PHY_HIGH_M                  GENMASK_ULL(39, 8)
 
 #define BYTES_PER_IDX_ADDR_L_U         8
 #define BYTES_PER_IDX_ADDR_L           4