clk: Fix typos

Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and
uses updated).

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index 84555a00f9501e9f1bffe6945149c9108c2254a7..17d75e8e2e8f34078b69d4a37f045bc0b238c78f 100644 (file)
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -405,7 +405,7 @@ static void ccu_div_clk_unregister(struct ccu_div_data *data, bool defer)
 {
        int idx;
 
-       /* Uninstall only the clocks registered on the specfied stage */
+       /* Uninstall only the clocks registered on the specified stage */
        for (idx = 0; idx < data->divs_num; ++idx) {
                if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
                        continue;

diff --git a/drivers/clk/baikal-t1/clk-ccu-pll.c b/drivers/clk/baikal-t1/clk-ccu-pll.c
index fce02ce77347a5f18e3b9ce635f2d3093df601f4..921b87024feb8e2e03b9a45a59f2a1568501c2a9 100644 (file)
--- a/drivers/clk/baikal-t1/clk-ccu-pll.c
+++ b/drivers/clk/baikal-t1/clk-ccu-pll.c
@@ -196,7 +196,7 @@ static void ccu_pll_clk_unregister(struct ccu_pll_data *data, bool defer)
 {
        int idx;
 
-       /* Uninstall only the clocks registered on the specfied stage */
+       /* Uninstall only the clocks registered on the specified stage */
        for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
                if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
                        continue;

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 5e7788406de39c94884cbc3aa162c378443322c0..02215ea794038fdaefdeb892659b9cd1cc33c91b 100644 (file)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1555,7 +1555,7 @@ static const char *const bcm2835_clock_osc_parents[] = {
        .parents = bcm2835_clock_osc_parents,                           \
        __VA_ARGS__)
 
-/* main peripherial parent mux */
+/* main peripheral parent mux */
 static const char *const bcm2835_clock_per_parents[] = {
        "gnd",
        "xosc",

diff --git a/drivers/clk/bcm/clk-bcm53573-ilp.c b/drivers/clk/bcm/clk-bcm53573-ilp.c
index 83ef41d618be37b8f621ef873b2d264367d9379a..b2fc05b607832c3f23b6353bc50afab89bd2fd6f 100644 (file)
--- a/drivers/clk/bcm/clk-bcm53573-ilp.c
+++ b/drivers/clk/bcm/clk-bcm53573-ilp.c
@@ -59,7 +59,7 @@ static unsigned long bcm53573_ilp_recalc_rate(struct clk_hw *hw,
        /*
         * At minimum we should loop for a bit to let hardware do the
         * measurement. This isn't very accurate however, so for a better
-        * precision lets try getting 20 different values for and use average.
+        * precision let's try getting 20 different values and use average.
         */
        while (num < 20) {
                regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &cur_val);

diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c
index aa89b4c9464e77fd1c7e36f1531fa8aee042e97a..79f3d37a0ee031aacfde8ceecd23cb5e6f173905 100644 (file)
--- a/drivers/clk/berlin/berlin2-avpll.c
+++ b/drivers/clk/berlin/berlin2-avpll.c
@@ -319,7 +319,7 @@ berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 
        /*
         * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide.
-        * AV2/AV3 form a fractional divider, where only specfic values for AV3
+        * AV2/AV3 form a fractional divider, where only specific values for AV3
         * are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass.
         */
        if (ch->index < 6) {

diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c
index 3432c801f1bd08a369c69084ed1382b0bf36d09f..595cfa533fb9b131031507ae0fe16f360ef9233f 100644 (file)
--- a/drivers/clk/clk-asm9260.c
+++ b/drivers/clk/clk-asm9260.c
@@ -92,8 +92,8 @@ static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
        { CLKID_SYS_CPU,        "cpu_div", "main_gate", HW_CPUCLKDIV },
        { CLKID_SYS_AHB,        "ahb_div", "cpu_div", HW_SYSAHBCLKDIV },
 
-       /* i2s has two deviders: one for only external mclk and internal
-        * devider for all clks. */
+       /* i2s has two dividers: one for only external mclk and internal
+        * divider for all clks. */
        { CLKID_SYS_I2S0M,      "i2s0m_div", "i2s0_mclk",  HW_I2S0MCLKDIV },
        { CLKID_SYS_I2S1M,      "i2s1m_div", "i2s1_mclk",  HW_I2S1MCLKDIV },
        { CLKID_SYS_I2S0S,      "i2s0s_div", "i2s0_gate",  HW_I2S0SCLKDIV },

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index faf88324f7b161c8e716cb33f16ebd7091dbfd2a..114afc13d640938451ae09acfacf699b44566f95 100644 (file)
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -92,7 +92,7 @@ static u8 soc_rev;
  *
  * There are some gates that do not have an associated reset; these are
  * handled by using -1 as the index for the reset, and the consumer must
- * explictly assert/deassert reset lines as required.
+ * explicitly assert/deassert reset lines as required.
  *
  * Clocks marked with CLK_IS_CRITICAL:
  *

diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index 934e53a96dddac8ed61dd109cfc188f3a2a0539a..31dc74d9d556d510dd67c6f730f940e403b6c309 100644 (file)
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -172,7 +172,7 @@ again:
                }
        }
 
-       /* Lets see if we find a better setting in fractional mode */
+       /* Let's see if we find a better setting in fractional mode */
        if (fract_shift == 0) {
                fract_shift = 3;
                goto again;

diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c
index f8417ee2961aaabc9c46e9007716d83b25a3c7bc..402ab74d9bfb2c55ac29cd50035f66cd4d674a8e 100644 (file)
--- a/drivers/clk/clk-clps711x.c
+++ b/drivers/clk/clk-clps711x.c
@@ -99,7 +99,7 @@ static void __init clps711x_clk_init_dt(struct device_node *np)
         */
        tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
        /* Timer2 in prescale mode.
-        * Value writen is automatically re-loaded when
+        * Value written is automatically re-loaded when
         * the counter underflows.
         */
        tmp |= SYSCON1_TC2M | SYSCON1_TC2S;

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 640c25788487f8cf6fb4431ed6fb612cf099f114..ea1c3d78e7cd47c2698483f58ae1d691ce6d399d 100644 (file)
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -131,7 +131,7 @@ struct eqc_early_match_data {
  * Both factors (mult and div) must fit in 32 bits. When an operation overflows,
  * this function throws away low bits so that factors still fit in 32 bits.
  *
- * Precision loss depends on amplitude of mult and div. Worst theorical
+ * Precision loss depends on amplitude of mult and div. Worst theoretical
  * loss is: (UINT_MAX+1) / UINT_MAX - 1 = 2.3e-10.
  * This is 1Hz every 4.3GHz.
  */

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 68e585a02fd90bd98715d5343d9c6f0c39ba7e01..4746f821913279212af7c4940b9b70de29f94ecf 100644 (file)
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -15,7 +15,7 @@
 #include <linux/string.h>
 
 /**
- * DOC: basic gatable clock which can gate and ungate its output
+ * DOC: basic gateable clock which can gate and ungate its output
  *
  * Traits of this clock:
  * prepare - clk_(un)prepare only ensures parent is (un)prepared

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 5d2a90addf1ab2d1a11a0fdb1b9008a982179f4f..921523fc26f2ece89b581006e115661575fc693a 100644 (file)
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -265,7 +265,7 @@ static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
                return -EINVAL;
 
        /*
-        * Program divider to div-by-1 if we succesfuly set core clock below
+        * Program divider to div-by-1 if we successfully set core clock below
         * 500MHz threshold.
         */
        if (rate <= CORE_IF_CLK_THRESHOLD_HZ)

diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index 8ddf3a9a53dfd5bb52a05a3e02788a357ea77ad3..d4e9c3577b35dec8d9ec67c489b7b5ae27211f55 100644 (file)
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -235,7 +235,7 @@ MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
  * through platform_device_id.
  *
  * However if device's DT node contains proper clock compatible and driver is
- * built as a module, then the *module* matching will be done trough DT aliases.
+ * built as a module, then the *module* matching will be done through DT aliases.
  * This requires of_device_id table.  In the same time this will not change the
  * actual *device* matching so do not add .of_match_table.
  */

diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index 15510c2ff21c0335f5cb30677343bd4ef59c0738..6a8f188629aa2d0cbf598c763c74a7cd610015d2 100644 (file)
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -451,7 +451,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
 
                /*
                 * Note that the scmi_clk_ops_db is on the stack, not global,
-                * because it cannot be shared between mulitple probe-sequences
+                * because it cannot be shared between multiple probe-sequences
                 * to avoid sharing the devm_ allocated clk_ops between multiple
                 * SCMI clk driver instances.
                 */

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index a4c92c5ef3ff749b5a07c8b86ee783307c73066d..e755db545e2eea51175fc84f39a5eacd37ea6514 100644 (file)
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -655,7 +655,7 @@ static int si5351_msynth_determine_rate(struct clk_hw *hw,
        unsigned long a, b, c;
        int divby4;
 
-       /* multisync6-7 can only handle freqencies < 150MHz */
+       /* multisync6-7 can only handle frequencies < 150MHz */
        if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
                rate = SI5351_MULTISYNTH67_MAX_FREQ;
 
@@ -1048,11 +1048,11 @@ static int si5351_clkout_determine_rate(struct clk_hw *hw,
        unsigned long rate = req->rate;
        unsigned char rdiv;
 
-       /* clkout6/7 can only handle output freqencies < 150MHz */
+       /* clkout6/7 can only handle output frequencies < 150MHz */
        if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
                rate = SI5351_CLKOUT67_MAX_FREQ;
 
-       /* clkout freqency is 8kHz - 160MHz */
+       /* clkout frequency is 8kHz - 160MHz */
        if (rate > SI5351_CLKOUT_MAX_FREQ)
                rate = SI5351_CLKOUT_MAX_FREQ;
        if (rate < SI5351_CLKOUT_MIN_FREQ)

diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
index c88650558f32db397014c029f1be26f55e7c4ef8..ca3473efa314b44b7eff6bc3ec9eafa518e0bd9e 100644 (file)
--- a/drivers/clk/clk-si544.c
+++ b/drivers/clk/clk-si544.c
@@ -39,7 +39,7 @@
 /* Max freq depends on speed grade */
 #define SI544_MIN_FREQ     200000U
 
-/* Si544 Internal oscilator runs at 55.05 MHz */
+/* Si544 Internal oscillator runs at 55.05 MHz */
 #define FXO              55050000U
 
 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */

diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c
index a549ea13be20de5b9f767b79d111ec54a8d177d8..e97fe90443a645c905465ad37cb5490c0c096834 100644 (file)
--- a/drivers/clk/clk-si570.c
+++ b/drivers/clk/clk-si570.c
@@ -63,7 +63,7 @@ struct clk_si570_info {
  * struct clk_si570:
  * @hw:        Clock hw struct
  * @regmap:    Device's regmap
- * @div_offset:        Rgister offset for dividers
+ * @div_offset:        Register offset for dividers
  * @info:      Device info
  * @fxtal:     Factory xtal frequency
  * @n1:                Clock divider N1
@@ -181,7 +181,7 @@ static int si570_update_rfreq(struct clk_si570 *data)
 }
 
 /**
- * si570_calc_divs() - Caluclate clock dividers
+ * si570_calc_divs() - Calculate clock dividers
  * @frequency: Target frequency
  * @data:      Driver data structure
  * @out_rfreq: RFREG fractional multiplier (output)

diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
index 7cb7d501d7a6ebffe002f80dfa937365e04d356a..95d66191df4bdb3609128ea097be896ef3a1038a 100644 (file)
--- a/drivers/clk/clk-sp7021.c
+++ b/drivers/clk/clk-sp7021.c
@@ -14,7 +14,7 @@
 
 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
 
-/* speical div_width values for PLLTV/PLLA */
+/* special div_width values for PLLTV/PLLA */
 #define DIV_TV         33
 #define DIV_A          34
 

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 85e23961ec3413ec1cb22b1f263b8e25052815ba..719cddc82ae6f8f706716e5ba91a69759c066415 100644 (file)
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -19,7 +19,7 @@
 #include <linux/mfd/syscon.h>
 
 /*
- * Include list of clocks wich are not derived from system clock (SYSCLOCK)
+ * Include list of clocks which are not derived from system clock (SYSCLOCK)
  * The index of these clocks is the secondary index of DT bindings
  *
  */

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 6d31cd54d7cfa7a0ac417ba7a1cfce93842c902c..4200022d20846038f02e191042da2a188c392402 100644 (file)
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -136,7 +136,7 @@
 #define VC5_MAX_FOD_NUM        4
 
 /* flags to describe chip features */
-/* chip has built-in oscilator */
+/* chip has built-in oscillator */
 #define VC5_HAS_INTERNAL_XTAL  BIT(0)
 /* chip has PFD requency doubler */
 #define VC5_HAS_PFD_FREQ_DBL   BIT(1)

diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
index f08feeaa3750bc86859294650de298762dea690a..70fcc30a13bf208f97dc0c8b1f428d6b0c7001c9 100644 (file)
--- a/drivers/clk/clk_test.c
+++ b/drivers/clk/clk_test.c
@@ -292,7 +292,7 @@ static void clk_test_set_set_get_rate(struct kunit *test)
 }
 
 /*
- * Test that clk_round_rate and clk_set_rate are consitent and will
+ * Test that clk_round_rate and clk_set_rate are consistent and will
  * return the same frequency.
  */
 static void clk_test_round_set_get_rate(struct kunit *test)

diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h
index 20bfcec2d3b58fd09dddd6b9ddac7394fe65de1f..ad286ba4ce0c6b63efd133edfb2228bcbff5566d 100644 (file)
--- a/drivers/clk/davinci/pll.h
+++ b/drivers/clk/davinci/pll.h
@@ -80,7 +80,7 @@ static const struct davinci_pll_sysclk_info n = {     \
  * @name: The name of the clock
  * @parent_names: Array of names of the parent clocks
  * @num_parents: Length of @parent_names
- * @table: Array of values to write to OCSEL[OCSRC] cooresponding to
+ * @table: Array of values to write to OCSEL[OCSRC] corresponding to
  *         @parent_names
  * @ocsrc_mask: Bitmask for OCSEL[OCSRC]
  */

diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
index 90d858522967c0627c6ea46aa8ce9783906a4870..21d4297f3225d0609e9945c282ed483cf7463244 100644 (file)
--- a/drivers/clk/hisilicon/clkgate-separated.c
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -17,9 +17,9 @@
 #include "clk.h"
 
 /* clock separated gate register offset */
-#define CLKGATE_SEPERATED_ENABLE               0x0
-#define CLKGATE_SEPERATED_DISABLE              0x4
-#define CLKGATE_SEPERATED_STATUS               0x8
+#define CLKGATE_SEPARATED_ENABLE               0x0
+#define CLKGATE_SEPARATED_DISABLE              0x4
+#define CLKGATE_SEPARATED_STATUS               0x8
 
 struct clkgate_separated {
        struct clk_hw   hw;
@@ -40,7 +40,7 @@ static int clkgate_separated_enable(struct clk_hw *hw)
                spin_lock_irqsave(sclk->lock, flags);
        reg = BIT(sclk->bit_idx);
        writel_relaxed(reg, sclk->enable);
-       readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+       readl_relaxed(sclk->enable + CLKGATE_SEPARATED_STATUS);
        if (sclk->lock)
                spin_unlock_irqrestore(sclk->lock, flags);
        return 0;
@@ -56,8 +56,8 @@ static void clkgate_separated_disable(struct clk_hw *hw)
        if (sclk->lock)
                spin_lock_irqsave(sclk->lock, flags);
        reg = BIT(sclk->bit_idx);
-       writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
-       readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+       writel_relaxed(reg, sclk->enable + CLKGATE_SEPARATED_DISABLE);
+       readl_relaxed(sclk->enable + CLKGATE_SEPARATED_STATUS);
        if (sclk->lock)
                spin_unlock_irqrestore(sclk->lock, flags);
 }
@@ -68,7 +68,7 @@ static int clkgate_separated_is_enabled(struct clk_hw *hw)
        u32 reg;
 
        sclk = container_of(hw, struct clkgate_separated, hw);
-       reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+       reg = readl_relaxed(sclk->enable + CLKGATE_SEPARATED_STATUS);
        reg &= BIT(sclk->bit_idx);
 
        return reg ? 1 : 0;
@@ -100,7 +100,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
        init.parent_names = (parent_name ? &parent_name : NULL);
        init.num_parents = (parent_name ? 1 : 0);
 
-       sclk->enable = reg + CLKGATE_SEPERATED_ENABLE;
+       sclk->enable = reg + CLKGATE_SEPARATED_ENABLE;
        sclk->bit_idx = bit_idx;
        sclk->flags = clk_gate_flags;
        sclk->hw.init = &init;

diff --git a/drivers/clk/imx/clk-fixup-div.c b/drivers/clk/imx/clk-fixup-div.c
index 6af8fd065fd3cd71b66713105aa68b3b19a22810..aa6addbeb5a8004db02f316a8793e5f990156968 100644 (file)
--- a/drivers/clk/imx/clk-fixup-div.c
+++ b/drivers/clk/imx/clk-fixup-div.c
@@ -18,7 +18,7 @@
  * @fixup: a hook to fixup the write value
  *
  * The imx fixup divider clock is a subclass of basic clk_divider
- * with an addtional fixup hook.
+ * with an additional fixup hook.
  */
 struct clk_fixup_div {
        struct clk_divider divider;

diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index b48701864ef01205d0759478665928223af525b3..418ac9fe2c269da3242a69c3758b2f627a9bc52b 100644 (file)
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -17,7 +17,7 @@
  * @fixup: a hook to fixup the write value
  *
  * The imx fixup multiplexer clock is a subclass of basic clk_mux
- * with an addtional fixup hook.
+ * with an additional fixup hook.
  */
 struct clk_fixup_mux {
        struct clk_mux mux;

diff --git a/drivers/clk/imx/clk-gate-exclusive.c b/drivers/clk/imx/clk-gate-exclusive.c
index 77342893bb719747ef1b50a40a8c5a88e554ca4d..7017e9d4e1882974f6310fab810182809f946dd3 100644 (file)
--- a/drivers/clk/imx/clk-gate-exclusive.c
+++ b/drivers/clk/imx/clk-gate-exclusive.c
@@ -18,7 +18,7 @@
  *     gate clock
  *
  * The imx exclusive gate clock is a subclass of basic clk_gate
- * with an addtional mask to indicate which other gate bits in the same
+ * with an additional mask to indicate which other gate bits in the same
  * register is mutually exclusive to this gate clock.
  */
 struct clk_gate_exclusive {

diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c
index b820449116031630630987dbae9915638d472b91..9c5f489b3975d66d3fa56bc4093cac4c79521d3f 100644 (file)
--- a/drivers/clk/imx/clk-imx5.c
+++ b/drivers/clk/imx/clk-imx5.c
@@ -454,7 +454,7 @@ static void __init mx51_clocks_init(struct device_node *np)
         * longer supported. Set to one for better power saving.
         *
         * The effect of not setting these bits is that MIPI clocks can't be
-        * enabled without the IPU clock being enabled aswell.
+        * enabled without the IPU clock being enabled as well.
         */
        val = readl(MXC_CCM_CCDR);
        val |= 1 << 18;

diff --git a/drivers/clk/imx/clk-imx8-acm.c b/drivers/clk/imx/clk-imx8-acm.c
index c169fe53a35f8355f10810a694e7e9b127fb5753..790f7e44b11e20e52fe3491c95f40bd0a463b278 100644 (file)
--- a/drivers/clk/imx/clk-imx8-acm.c
+++ b/drivers/clk/imx/clk-imx8-acm.c
@@ -22,7 +22,7 @@
  * struct clk_imx_acm_pm_domains - structure for multi power domain
  * @pd_dev: power domain device
  * @pd_dev_link: power domain device link
- * @num_domains: power domain nummber
+ * @num_domains: power domain number
  */
 struct clk_imx_acm_pm_domains {
        struct device **pd_dev;

diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index 77c4cde8a72bd71653bbd2e95148bc1357ec1aae..6aa8cc9390284a2490f6cf649711c93b6eeebd75 100644 (file)
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -711,7 +711,7 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
        if (ret)
                goto put_device;
 
-       /* For API backwards compatiblilty, simply return NULL for success */
+       /* For API backwards compatibility, simply return NULL for success */
        return NULL;
 
 put_device:

diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 99da9bd86e63e3ef4554c0ac6fe32c10afe63fe8..0d417d69dab7199b9e4145aa3e88ebaf99f60510 100644 (file)
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -239,7 +239,7 @@ ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
  *
  * Register the clocks described by the CGU with the common clock framework.
  *
- * Return: 0 on success or -errno if unsuccesful.
+ * Return: 0 on success or -errno if unsuccessful.
  */
 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
 

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 448eece246ca752da576d257b33f822ec92f4192..663de28e315be41ab8179626ce10cd698ed979fd 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -918,7 +918,7 @@ static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
        /*
         * Following these parent clocks, we should also have had mpll2, mpll3
         * and gp0_pll but these clocks are too precious to be used here. All
-        * the necessary rates for MMC and NAND operation can be acheived using
+        * the necessary rates for MMC and NAND operation can be achieved using
         * xtal or fclk_div clocks
         */
 };

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index d9e546e006d7e0b2af92fbcbb35498a00bd2fc6d..72767bc447156b56f987a966e7f3752beb88f03d 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -2489,7 +2489,7 @@ static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
        /*
         * Following these parent clocks, we should also have had mpll2, mpll3
         * and gp0_pll but these clocks are too precious to be used here. All
-        * the necessary rates for MMC and NAND operation can be acheived using
+        * the necessary rates for MMC and NAND operation can be achieved using
         * g12a_ee_core or fclk_div clocks
         */
 };
@@ -3753,8 +3753,8 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
 };
 
 /*
- * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value
- * when setting a clock whith this node in the clock path, but doesn't garantee the divider
+ * FIXME: Force as bypass by forcing a single /1 table entry, and doesn't on boot value
+ * when setting a clock with this node in the clock path, but doesn't guarantee the divider
  * is at /1 at boot until a rate is set.
  */
 static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 3abb44a2532b9e4ef9259eebce836226ac25e1db..9fcf026fc491e2b122dcfe34cabbc165dd71bc0b 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1335,7 +1335,7 @@ static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
        /*
         * Following these parent clocks, we should also have had mpll2, mpll3
         * and gp0_pll but these clocks are too precious to be used here. All
-        * the necessary rates for MMC and NAND operation can be acheived using
+        * the necessary rates for MMC and NAND operation can be achieved using
         * xtal or fclk_div clocks
         */
 };

diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
index 1b4f023cdc8be44c4a57f0d2924c280b5c70d674..6fbc6dc50ca3d9f1f0aecc5e43f4d41f23cb371a 100644 (file)
--- a/drivers/clk/microchip/clk-core.c
+++ b/drivers/clk/microchip/clk-core.c
@@ -326,7 +326,7 @@ static void roclk_calc_div_trim(unsigned long rate,
         * i.e. fout = fin / 2 * DIV
         *      whereas DIV = rodiv + (rotrim / 512)
         *
-        * Since kernel does not perform floating-point arithmatic so
+        * Since kernel does not perform floating-point arithmetic so
         * (rotrim/512) will be zero. And DIV & rodiv will result same.
         *
         * ie. fout = (fin * 256) / [(512 * rodiv) + rotrim]  ... from (1)

diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
index 350eeb3e9e25a96c8b31b78543d59bb1c6bd6a7b..6855815ee8bef9c94b8b9c3946a43d2a58e02b24 100644 (file)
--- a/drivers/clk/mmp/clk-gate.c
+++ b/drivers/clk/mmp/clk-gate.c
@@ -15,7 +15,7 @@
 #include "clk.h"
 
 /*
- * Some clocks will have mutiple bits to enable the clocks, and
+ * Some clocks will have multiple bits to enable the clocks, and
  * the bits to disable the clock is not same as enabling bits.
  */
 

diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index 45665655a2583e9424ebee9a0b5405071c918220..8d31a595a27c13006212ed26774eb31f4bd3eb7b 100644 (file)
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -7,7 +7,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Andrew Lunn <andrew@lunn.ch>
- *
  */
 
 #include <linux/kernel.h>
@@ -19,8 +18,8 @@
 /*
  * Core Clocks
  *
- * Armada XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
+ * Armada XP Sample At Reset is a 64 bit bitfield split in two
+ * registers of 32 bits
  */
 
 #define SARL                           0       /* Low part [0:31] */

diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
index 928e8b1c46a15f8a4aae288e6b6ac207c48def24..0a78ef380646690938c352796fad8a13b086267a 100644 (file)
--- a/drivers/clk/mxs/clk-div.c
+++ b/drivers/clk/mxs/clk-div.c
@@ -16,7 +16,7 @@
  * @busy: busy bit shift
  *
  * The mxs divider clock is a subclass of basic clk_divider with an
- * addtional busy bit.
+ * additional busy bit.
  */
 struct clk_div {
        struct clk_divider divider;

diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
index ddb28b38f54931d6d5cf65ea5ec08b2bfdf0f7ce..751b786d73f83b6c76f7bc17f699732f4eba8fb3 100644 (file)
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c
@@ -148,7 +148,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
                val |= LPC18XX_CCU_RUN;
        } else {
                /*
-                * To safely disable a branch clock a squence of two separate
+                * To safely disable a branch clock a sequence of two separate
                 * writes must be used. First write should set the AUTO bit
                 * and the next write should clear the RUN bit.
                 */

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index cefceb780889e92e7762e701c44c5f06511bf6db..a93d1f412a7b6a099965afef3d173d526cb7a0fd 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -1245,7 +1245,7 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
 };
 
 /*
- * Clock ON depends on external parent 'config noc', so cant poll
+ * Clock ON depends on external parent 'config noc', so can't poll
  * delay and also mark as crtitical for camss boot
  */
 static struct clk_branch gcc_camera_ahb_clk = {
@@ -1398,7 +1398,7 @@ static struct clk_branch gcc_ddrss_gpu_axi_clk = {
 };
 
 /*
- * Clock ON depends on external parent 'config noc', so cant poll
+ * Clock ON depends on external parent 'config noc', so can't poll
  * delay and also mark as crtitical for disp boot
  */
 static struct clk_branch gcc_disp_ahb_clk = {
@@ -3339,7 +3339,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
 };
 
 /*
- * Clock ON depends on external parent 'config noc', so cant poll
+ * Clock ON depends on external parent 'config noc', so can't poll
  * delay and also mark as crtitical for video boot
  */
 static struct clk_branch gcc_video_ahb_clk = {

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 398a226ad34ea2793d674c1ae29fdb2d3750e8ab..dcc9dcb597ae11d59900a46591826fe82a5ea132 100644 (file)
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -16,14 +16,14 @@
  * of the SoC or supplied after the SoC characterization.
  *
  * The below implementation of the CPU clock allows the rate changes of the CPU
- * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * clock and the corresponding rate changes of the auxiliary clocks of the CPU
  * domain. The platform clock driver provides a clock register configuration
  * for each configurable rate which is then used to program the clock hardware
- * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * registers to achieve a fast co-oridinated rate change for all the CPU domain
  * clocks.
  *
  * On a rate change request for the CPU clock, the rate change is propagated
- * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * up to the PLL supplying the clock to the CPU domain clock blocks. While the
  * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
  * alternate clock source. If required, the alternate clock source is divided
  * down in order to keep the output clock rate within the previous OPP limits.

diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
index b3ed8e7523e50f4fd5cab69353e94bb1d6949e2e..8b1292c5686312cc649252edc865e49ce88cc8b3 100644 (file)
--- a/drivers/clk/rockchip/clk-mmc-phase.c
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -174,11 +174,11 @@ static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,
 
        /*
         * rockchip_mmc_clk is mostly used by mmc controllers to sample
-        * the intput data, which expects the fixed phase after the tuning
+        * the input data, which expects the fixed phase after the tuning
         * process. However if the clock rate is changed, the phase is stale
         * and may break the data sampling. So here we try to restore the phase
         * for that case, except that
-        * (1) cached_phase is invaild since we inevitably cached it when the
+        * (1) cached_phase is invalid since we inevitably cached it when the
         * clock provider be reparented from orphan to its real parent in the
         * first place. Otherwise we may mess up the initialization of MMC cards
         * since we only set the default sample phase and drive phase later on.

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index af74439a74574bb232f496d8c51cf42516eefe1c..c9d599c31923fc6a7f6a25a2296cd5853c881c60 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -68,7 +68,7 @@ static long rockchip_pll_round_rate(struct clk_hw *hw,
        const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
        int i;
 
-       /* Assumming rate_table is in descending order */
+       /* Assuming rate_table is in descending order */
        for (i = 0; i < pll->rate_count; i++) {
                if (drate >= rate_table[i].rate)
                        return rate_table[i].rate;

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 1e9c3c0d31e39dcf10bf0ae8453c3a8d9cc66dc4..7c5e74c7a2e210970a5a48b736e390c77e47399d 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -532,7 +532,7 @@ struct rockchip_pll_rate_table {
  *
  * Flags:
  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
- *     rate_table parameters and ajust them if necessary.
+ *     rate_table parameters and adjust them if necessary.
  * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
  */
 struct rockchip_pll_clock {

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 97982662e1a684180e061f06e4a5ccba43fbdb92..4e1ebd8a30b1b422e33a4bb4527006e36c41666f 100644 (file)
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -243,7 +243,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
                if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
                        /*
                         * In Exynos4210, ATB clock parent is also mout_core. So
-                        * ATB clock also needs to be mantained at safe speed.
+                        * ATB clock also needs to be maintained at safe speed.
                         */
                        alt_div |= E4210_DIV0_ATB_MASK;
                        alt_div_mask |= E4210_DIV0_ATB_MASK;

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index fe8abe442c519930027612d8dd842920074218ef..e4faf02b631e07dea69be0bb7d141f52fa9900ae 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -56,7 +56,7 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
        const struct samsung_pll_rate_table *rate_table = pll->rate_table;
        int i;
 
-       /* Assumming rate_table is in descending order */
+       /* Assuming rate_table is in descending order */
        for (i = 0; i < pll->rate_count; i++) {
                if (drate >= rate_table[i].rate)
                        return rate_table[i].rate;

diff --git a/drivers/clk/sophgo/clk-sg2042-clkgen.c b/drivers/clk/sophgo/clk-sg2042-clkgen.c
index a334963e83ce5ecbae206861695c99ec503ab034..9e61288d34f3757315702c355f2669577b29676f 100644 (file)
--- a/drivers/clk/sophgo/clk-sg2042-clkgen.c
+++ b/drivers/clk/sophgo/clk-sg2042-clkgen.c
@@ -968,7 +968,7 @@ static int sg2042_mux_notifier_cb(struct notifier_block *nb,
                /*
                 * "1" is the array index of the second parent input source of
                 * mux. For SG2042, it's fpll for all mux clocks.
-                * "0" is the array index of the frist parent input source of
+                * "0" is the array index of the first parent input source of
                 * mux, For SG2042, it's mpll.
                 * FIXME, any good idea to avoid magic number?
                 */

diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 361d344bfaf05afd76fdead0f49c856a97c732b5..fdfb26c671888dc73fa61db139fddff75351f02f 100644 (file)
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -199,7 +199,7 @@ static struct frac_rate_tbl amba_synth_rtbl[] = {
  * We can program this synthesizer to make cpu run on different clock
  * frequencies.
  * Following table provides configuration values to let cpu run on 200,
- * 250, 332, 400 or 500 MHz considering different possibilites of input
+ * 250, 332, 400 or 500 MHz considering different possibilities of input
  * (vco1div2) clock.
  *
  * --------------------------------------------------------------------

diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
index e738dafa4fe910fa96b617fc782551dc3f2806c8..775519eb1cb6a5720bfe1a594adfd7e00c5476e9 100644 (file)
--- a/drivers/clk/sprd/gate.h
+++ b/drivers/clk/sprd/gate.h
@@ -26,7 +26,7 @@ struct sprd_gate {
  * CLK_GATE_BIG_ENDIAN         BIT(2)
  * so we define new flags from BIT(3)
  */
-#define SPRD_GATE_NON_AON BIT(3) /* not alway powered on, check before read */
+#define SPRD_GATE_NON_AON BIT(3) /* not always powered on, check before read */
 
 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,     \
                                    _sc_offset, _enable_mask, _flags,   \

diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index 9384ecc6c7413867c432623377091857946acad5..f763d83de9eeada67e4f062c0e49694b581d4bb8 100644 (file)
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -1550,7 +1550,7 @@ static struct sprd_clk_desc ums512_aon_gate_desc = {
 
 /* audcp apb gates */
 /* Audcp apb clocks configure CLK_IGNORE_UNUSED because these clocks may be
- * controlled by audcp sys at the same time. It may be cause an execption if
+ * controlled by audcp sys at the same time. It may cause an exception if
  * kernel gates these clock.
  */
 static SPRD_SC_GATE_CLK_HW(audcp_wdg_eb, "audcp-wdg-eb",
@@ -1592,7 +1592,7 @@ static const struct sprd_clk_desc ums512_audcpapb_gate_desc = {
 
 /* audcp ahb gates */
 /* Audcp aphb clocks configure CLK_IGNORE_UNUSED because these clocks may be
- * controlled by audcp sys at the same time. It may be cause an execption if
+ * controlled by audcp sys at the same time. It may cause an exception if
  * kernel gates these clock.
  */
 static SPRD_SC_GATE_CLK_HW(audcp_iis0_eb, "audcp-iis0-eb",

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index e9d8168d02b83296d757ba918e842d515916bb99..52833d4241c5f3c95ca26e189ce061359df37f6d 100644 (file)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -376,7 +376,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
 
 /*
  * This clock notifier is called when the rate of PLL0 clock is to be changed.
- * The cpu_root clock should save the curent parent clock and switch its parent
+ * The cpu_root clock should save the current parent clock and switch its parent
  * clock to osc before PLL0 rate will be changed. Then switch its parent clock
  * back after the PLL0 rate is completed.
  */

diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 5fcc4c77c11f27dd3f733c9b5fb523fff773d007..b8b45ed22f981df580506f3d4ca801ba11d2bab2 100644 (file)
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -2041,7 +2041,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
        KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
 
-       /* Particulary Kernel Clocks (no mux or no gate) */
+       /* Particularly Kernel Clocks (no mux or no gate) */
        MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
        MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
        MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index acb4e8b9b1bae9b902e9fd414e2d91004aa73b10..d24fa344930308e2907bc21cfeaa01ef976bf6fe 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -80,7 +80,7 @@ static struct ccu_div r_apb2_clk = {
  * in the BSP source code, although most of them are unused. The existence
  * of the hardware block is verified with "3.1 Memory Mapping" chapter in
  * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
- * with "3.3.2.1 System Bus Tree" chapter inthe same document.
+ * with "3.3.2.1 System Bus Tree" chapter in the same document.
  */
 static SUNXI_CCU_GATE(r_apb1_timer_clk,        "r-apb1-timer", "r-apb1",
                      0x11c, BIT(0), 0);

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 8b729c9b3545c87fae572f04b72e27e51cc1b7e2..44565830881dd8e90c6731e696eaf62d1b711098 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2",     "apb2",
 static SUNXI_CCU_GATE(bus_i2c3_clk,    "bus-i2c3",     "apb2",
                      0x06c, BIT(3), 0);
 /*
- * In datasheet here's "Reserved", however the gate exists in BSP soucre
+ * In datasheet here's "Reserved", however the gate exists in BSP source
  * code.
  */
 static SUNXI_CCU_GATE(bus_can_clk,     "bus-can",      "apb2",

diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 88ed89658d4579ddb99235e4cc10ddb4bc1528c6..c7e00f0c29a5562391452381c531e376edcad900 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -66,7 +66,7 @@ EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, "SUNXI_CCU");
  * changed. In common PLL designs, changes to the dividers take effect
  * almost immediately, while changes to the multipliers (implemented
  * as dividers in the feedback loop) take a few cycles to work into
- * the feedback loop for the PLL to stablize.
+ * the feedback loop for the PLL to stabilize.
  *
  * Sometimes when the PLL clock rate is changed, the decrease in the
  * divider is too much for the decrease in the multiplier to catch up.

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index a3488aaac3f78f040722357a197b766a5d80825f..412902f573b54d55c57c0d76c4e26ce9811bd5f0 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -255,7 +255,7 @@
 /* VIC register to handle during MBIST WAR */
 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
 
-/* APE, DISPA and VIC base addesses needed for MBIST WAR */
+/* APE, DISPA and VIC base addresses needed for MBIST WAR */
 #define TEGRA210_AHUB_BASE  0x702d0000
 #define TEGRA210_DISPA_BASE 0x54200000
 #define TEGRA210_VIC_BASE  0x54340000

diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 27e6b9cb188179a298bc64fe0874f8c9d1cba2ea..a99aaf2e768421c351e7817570603eff1a87803c 100644 (file)
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -30,7 +30,7 @@ static LIST_HEAD(autoidle_clks);
 
 /*
  * we have some non-atomic read/write
- * operations behind it, so lets
+ * operations behind it, so let's
  * take one lock for handling autoidle
  * of all clocks
  */

diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index f24f6eb2157ae1cf21a85bf7c160a2c7ce54795e..35af3079c0022373a7b22c267a5d49fa5a13555d 100644 (file)
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -286,7 +286,7 @@ int __init am43xx_dt_clk_init(void)
        /*
         * cpsw_cpts_rft_clk  has got the choice of 3 clocksources
         * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
-        * By default dpll_core_m4_ck is selected, witn this as clock
+        * By default dpll_core_m4_ck is selected, with this as clock
         * source the CPTS doesnot work properly. It gives clockcheck errors
         * while running PTP.
         * clockcheck: clock jumped backward or running slower than expected!

diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index f684fc306eccd76b4e38ff65e96114167feca392..d6d247ff2be59de373ec855c4aff2931041b5085 100644 (file)
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -84,7 +84,7 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 }
 
 /**
- * clk_mux_save_context - Save the parent selcted in the mux
+ * clk_mux_save_context - Save the parent selected in the mux
  * @hw: pointer  struct clk_hw
  *
  * Save the parent mux value.

diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index d5cb372f0901c0ae637de88e0025560db8db96e8..b69c3fbdfbce66876d5b1d4faaf4050759e44561 100644 (file)
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -194,7 +194,7 @@ static int vco_set(struct clk_icst *icst, struct icst_vco vco)
                        pr_err("ICST error: tried to use RDW != 22\n");
                break;
        default:
-               /* Regular auxilary oscillator */
+               /* Regular auxiliary oscillator */
                mask = VERSATILE_AUX_OSC_BITS;
                val = vco.v | (vco.r << 9) | (vco.s << 16);
                break;

diff --git a/drivers/clk/visconti/pll.c b/drivers/clk/visconti/pll.c
index 3f929cf8dd2f71d5a57986b917c86fa4fc9e0ffd..8ca1bad61864204027b7aff9020f1cb9e7d198d3 100644 (file)
--- a/drivers/clk/visconti/pll.c
+++ b/drivers/clk/visconti/pll.c
@@ -107,7 +107,7 @@ static long visconti_pll_round_rate(struct clk_hw *hw,
        const struct visconti_pll_rate_table *rate_table = pll->rate_table;
        int i;
 
-       /* Assumming rate_table is in descending order */
+       /* Assuming rate_table is in descending order */
        for (i = 0; i < pll->rate_count; i++)
                if (rate >= rate_table[i].rate)
                        return rate_table[i].rate;