clk: renesas: r9a09g057: Add entries for CANFD

Add clock and reset entries for the CANFD IP.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224165049.3384870-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 991f9a2ec12e8d209695f265d19770a3727bb8e7..6943cad318b5d7dfb612152669f1c03e4db4c36b 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -46,6 +46,7 @@ enum clk_ids {
        CLK_PLLCLN_DIV2,
        CLK_PLLCLN_DIV8,
        CLK_PLLCLN_DIV16,
+       CLK_PLLCLN_DIV20,
        CLK_PLLCLN_DIV64,
        CLK_PLLCLN_DIV256,
        CLK_PLLCLN_DIV1024,
@@ -185,6 +186,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
        DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
        DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
+       DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
        DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
        DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
        DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
@@ -440,6 +442,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(1, BIT(7))),
        DEF_MOD("riic_7_ckm",                   CLK_PLLCLN_DIV16, 9, 11, 4, 27,
                                                BUS_MSTOP(1, BIT(8))),
+       DEF_MOD("canfd_0_pclk",                 CLK_PLLCLN_DIV16, 9, 12, 4, 28,
+                                               BUS_MSTOP(10, BIT(14))),
+       DEF_MOD("canfd_0_clk_ram",              CLK_PLLCLN_DIV8, 9, 13, 4, 29,
+                                               BUS_MSTOP(10, BIT(14))),
+       DEF_MOD("canfd_0_clkc",                 CLK_PLLCLN_DIV20, 9, 14, 4, 30,
+                                               BUS_MSTOP(10, BIT(14))),
        DEF_MOD("spi_hclk",                     CLK_PLLCM33_GEAR, 9, 15, 4, 31,
                                                BUS_MSTOP(4, BIT(5))),
        DEF_MOD("spi_aclk",                     CLK_PLLCM33_GEAR, 10, 0, 5, 0,
@@ -634,6 +642,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(9, 14, 4, 15),          /* RIIC_6_MRST */
        DEF_RST(9, 15, 4, 16),          /* RIIC_7_MRST */
        DEF_RST(10, 0, 4, 17),          /* RIIC_8_MRST */
+       DEF_RST(10, 1, 4, 18),          /* CANFD_0_RSTP_N */
+       DEF_RST(10, 2, 4, 19),          /* CANFD_0_RSTC_N */
        DEF_RST(10, 3, 4, 20),          /* SPI_HRESETN */
        DEF_RST(10, 4, 4, 21),          /* SPI_ARESETN */
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */