soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack one

The UBWC 1.0 case is easy - it must be all 3 enabled.
UBWC2.0 and 3.x require that level1 is removed, follow suit.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660983/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 816bad6674ab6fc61ba0d9ca5d8581f2b61e53a6..bd0a98aad9f3b222abcf0a7af85a318caffa9841 100644 (file)
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -15,12 +15,18 @@
 static const struct qcom_ubwc_cfg_data msm8937_data = {
        .ubwc_enc_version = UBWC_1_0,
        .ubwc_dec_version = UBWC_1_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
+                       UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 14,
 };
 
 static const struct qcom_ubwc_cfg_data msm8998_data = {
        .ubwc_enc_version = UBWC_1_0,
        .ubwc_dec_version = UBWC_1_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
+                       UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 15,
 };
 
@@ -70,6 +76,8 @@ static const struct qcom_ubwc_cfg_data sc7280_data = {
 static const struct qcom_ubwc_cfg_data sc8180x_data = {
        .ubwc_enc_version = UBWC_3_0,
        .ubwc_dec_version = UBWC_3_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 16,
        .macrotile_mode = true,
 };
@@ -87,12 +95,16 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = {
 static const struct qcom_ubwc_cfg_data sdm670_data = {
        .ubwc_enc_version = UBWC_2_0,
        .ubwc_dec_version = UBWC_2_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 14,
 };
 
 static const struct qcom_ubwc_cfg_data sdm845_data = {
        .ubwc_enc_version = UBWC_2_0,
        .ubwc_dec_version = UBWC_2_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 15,
 };
 
@@ -118,6 +130,8 @@ static const struct qcom_ubwc_cfg_data sm6125_data = {
 static const struct qcom_ubwc_cfg_data sm6150_data = {
        .ubwc_enc_version = UBWC_2_0,
        .ubwc_dec_version = UBWC_2_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 14,
 };
 
@@ -133,12 +147,16 @@ static const struct qcom_ubwc_cfg_data sm6350_data = {
 static const struct qcom_ubwc_cfg_data sm7150_data = {
        .ubwc_enc_version = UBWC_2_0,
        .ubwc_dec_version = UBWC_2_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 14,
 };
 
 static const struct qcom_ubwc_cfg_data sm8150_data = {
        .ubwc_enc_version = UBWC_3_0,
        .ubwc_dec_version = UBWC_3_0,
+       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+                       UBWC_SWIZZLE_ENABLE_LVL3,
        .highest_bank_bit = 15,
 };