}
};
+static const struct camss_subdev_resources csiphy_res_sm6150[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy-1p2", .init_load_uA = 35000 },
+ { .supply = "vdd-csiphy-1p8", .init_load_uA = 5000 }
+ },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm6150[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "vfe0_cphy_rx", "vfe0_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "vfe1_cphy_rx", "vfe1_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_cphy_rx", "vfe_lite_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid_lite" },
+ .interrupt = { "csid_lite" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_sm6150[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe0", "vfe0_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe1", "vfe1_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 } },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_sm6150[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
.vfe_num = ARRAY_SIZE(vfe_res_845),
};
+static const struct camss_resources sm6150_resources = {
+ .version = CAMSS_6150,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm6150,
+ .csid_res = csid_res_sm6150,
+ .vfe_res = vfe_res_sm6150,
+ .icc_res = icc_res_sm6150,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm6150),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm6150),
+ .csid_num = ARRAY_SIZE(csid_res_sm6150),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm6150),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
+ { .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },