arm64: dts: rockchip: Add OPP data for CPU cores on RK3588

By default the CPUs on RK3588 start up in a conservative performance
mode. Add frequency and voltage mappings to the device tree to enable
dynamic scaling via cpufreq.

OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
stripping them down to the minimum frequency and voltage combinations
as expected by the generic upstream cpufreq-dt driver, and also dropping
those OPPs that don't differ in voltage but only in frequency (keeping
the top frequency OPP in each case).

Note that this patch ignores voltage scaling for the CPU memory
interface which the downstream kernel does through a custom cpufreq
driver, and which is why the downstream version has two sets of voltage
values for each OPP (the second one being meant for the memory
interface supply regulator). This is done instead via regulator
coupling between CPU and memory interface supplies on affected boards.

This has been tested on Rock 5B with u-boot 2023.11 compiled from
Collabora's integration tree [2] with binary bl31 and appears to be
stable both under active cooling and passive cooling (with throttling)

[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
new file mode 100644 (file)
index 0000000..35bbc3c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+       cluster0_opp_table: opp-table-cluster0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1008000000 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <675000 675000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <712500 712500 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <762500 762500 950000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <850000 850000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <950000 950000 950000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+
+       cluster1_opp_table: opp-table-cluster1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <675000 675000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <725000 725000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <762500 762500 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <850000 850000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2016000000 {
+                       opp-hz = /bits/ 64 <2016000000>;
+                       opp-microvolt = <925000 925000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2208000000 {
+                       opp-hz = /bits/ 64 <2208000000>;
+                       opp-microvolt = <987500 987500 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2400000000 {
+                       opp-hz = /bits/ 64 <2400000000>;
+                       opp-microvolt = <1000000 1000000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+
+       cluster2_opp_table: opp-table-cluster2 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <675000 675000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <725000 725000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <762500 762500 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <850000 850000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2016000000 {
+                       opp-hz = /bits/ 64 <2016000000>;
+                       opp-microvolt = <925000 925000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2208000000 {
+                       opp-hz = /bits/ 64 <2208000000>;
+                       opp-microvolt = <987500 987500 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-2400000000 {
+                       opp-hz = /bits/ 64 <2400000000>;
+                       opp-microvolt = <1000000 1000000 1000000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+};
+
+&cpu_b0 {
+       operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b1 {
+       operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b2 {
+       operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_b3 {
+       operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_l0 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l1 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l2 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l3 {
+       operating-points-v2 = <&cluster0_opp_table>;
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 0bbeee399a63bb5481286f9115ef601ed758308a..7462cc1e1007fb15a69c2ecb91c5aee533f6f37d 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -5,3 +5,4 @@
  */
 
 #include "rk3588-extra.dtsi"
+#include "rk3588-opp.dtsi"

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index a379269147c43294b841b7d43a16cee20100e594..c7fecf8fe7ec385a62a7549b4edcd010fe3a235f 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -5,3 +5,4 @@
  */
 
 #include "rk3588-base.dtsi"
+#include "rk3588-opp.dtsi"