[AArch64,PATCH] Adjust preferred_reload_class of SP+C

Co-Authored-By: Marcus Shawcroft <marcus.shawcroft@arm.com>
From-SVN: r204018

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bb4158a9511ae7831baa64bed4061b8d66485af0..60a9547df817a1f153690e71de1b74186fa2d8ac 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-10-17  Ian Bolton  <ian.bolton@arm.com>
+           Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_preferred_reload_class):
+       Special case reload SP+C into none GENERAL_REGS.
+
 2013-10-24  Michael Matz  <matz@suse.de>
 
        * gengtype.c (is_file_equal): Check that files will be same

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index d553af87dc667edb6824c513943cf72eb07fe9d4..83d0c66706062c311cf24be248ba9541c973c48e 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4263,6 +4263,24 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
       && !aarch64_simd_imm_scalar_p (x, GET_MODE (x)))
     return NO_REGS;
 
+  /* Register eliminiation can result in a request for
+     SP+constant->FP_REGS.  We cannot support such operations which
+     use SP as source and an FP_REG as destination, so reject out
+     right now.  */
+  if (! reg_class_subset_p (regclass, GENERAL_REGS) && GET_CODE (x) == PLUS)
+    {
+      rtx lhs = XEXP (x, 0);
+
+      /* Look through a possible SUBREG introduced by ILP32.  */
+      if (GET_CODE (lhs) == SUBREG)
+       lhs = SUBREG_REG (lhs);
+
+      gcc_assert (REG_P (lhs));
+      gcc_assert (reg_class_subset_p (REGNO_REG_CLASS (REGNO (lhs)),
+                                     POINTER_REGS));
+      return NO_REGS;
+    }
+
   return regclass;
 }