mips.h (mips_tune_attr): New macro.

	* config/mips/mips.h (mips_tune_attr): New macro.
	* config/mips/mips.md (cpu): Use it.

From-SVN: r146357

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 48f1f6c7b3bcd47a6636f52228d82276288349d0..a7dcc8ed6db72b9012aa89d4b7f89c5a69af1c41 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2009-04-19  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * config/mips/mips.h (mips_tune_attr): New macro.
+       * config/mips/mips.md (cpu): Use it.
+
 2009-04-19  Joseph Myers  <joseph@codesourcery.com>
 
        PR c/38243

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 6fac454d61d915cfee72a0966ca34f8070199d73..cd6f1e5d2202662cd64b89bcd3b80833f55fdde2 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3463,3 +3463,7 @@ extern enum mips_code_readable_setting mips_code_readable;
 
 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)     \
   mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+/* This is necessary to avoid a warning about comparing different enum
+   types.  */
+#define mips_tune_attr ((enum attr_cpu) mips_tune)

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 8a6719466d3ba4fac3d3ac47fff1ce91966a064a..8453aab3debad93a89453d82cb855adea52c7e39 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -571,7 +571,7 @@
 ;; with the processor_type enumeration in mips.h.
 (define_attr "cpu"
   "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
-  (const (symbol_ref "mips_tune")))
+  (const (symbol_ref "mips_tune_attr")))
 
 ;; The type of hardware hazard associated with this instruction.
 ;; DELAY means that the next instruction cannot read the result