s390.md ("*llgt_sisi", [...]): New insns.

	* config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
	"*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.

From-SVN: r70812

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 481a92659b6d8d79775b5d2ab2b4c1da0d702154..8fb59454caac1ed42e42473861383ec5f93ca7cc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-26  Andreas Krebbel <krebbel1@de.ibm.com>
+
+       * config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
+       "*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.
+
 2003-08-26  Andreas Krebbel <krebbel1@de.ibm.com>
 
        * config/s390/s390.md ("*fmadddf", "*fmsubdf", 

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index d9e65439af069cf1be85e55b0471322ad75da2e1..fa7203df47abf69275a1df5c9e8419bd768ce80d 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2439,6 +2439,77 @@
   "llgh\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
+;
+; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
+;
+
+(define_insn "*llgt_sisi"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+               (const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_sisi_split"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+               (const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:SI (match_dup 1)
+               (const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_didi"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%N1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_didi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (match_dup 1)
+                (const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_sidi"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+               (const_int 2147483647)))]
+  "TARGET_64BIT"
+  "llgt\t%0,%1"
+  [(set_attr "op_type"  "RXE")])
+
+(define_insn_and_split "*llgt_sidi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) 
+               (const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (subreg:DI (match_dup 1) 0) 
+               (const_int 2147483647)))]
+  "")
+
 ;
 ; zero_extendqidi2 instruction pattern(s)
 ;