drm/msm/disp/dpu: add merge3d support for sc7280

On SC7280 targets, display modes with a width greater than the
max_mixer_width (2400) are rejected during mode validation when
merge3d is disabled. This limitation exists because, without a
3D merge block, two layer mixers cannot be combined(non-DSC interface),
preventing large layers from being split across mixers. As a result,
higher resolution modes cannot be supported.

Enable merge3d support on SC7280 to allow combining streams from
two layer mixers into a single non-DSC interface. This capability
removes the width restriction and enables buffer sizes beyond the
2400-pixel limit.

Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 target")
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696713/
Link: https://lore.kernel.org/r/20260101-4k-v2-1-712ae3c1f816@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 8f978b9c345202d3ea1a7781e4ef2763b46c6f6e..2f8688224f3430ff6d2aa80836b72262ed5b7058 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
        .has_dim_layer = true,
        .has_idle_pc = true,
        .max_linewidth = 2400,
+       .has_3d_merge = true,
        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
 
@@ -134,17 +135,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
                .name = "pingpong_2", .id = PINGPONG_2,
                .base = 0x6b000, .len = 0,
                .sblk = &sc7280_pp_sblk,
-               .merge_3d = 0,
+               .merge_3d = MERGE_3D_1,
                .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
        }, {
                .name = "pingpong_3", .id = PINGPONG_3,
                .base = 0x6c000, .len = 0,
                .sblk = &sc7280_pp_sblk,
-               .merge_3d = 0,
+               .merge_3d = MERGE_3D_1,
                .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
        },
 };
 
+static const struct dpu_merge_3d_cfg sc7280_merge_3d[] = {
+       {
+               .name = "merge_3d_1", .id = MERGE_3D_1,
+               .base = 0x4f000, .len = 0x8,
+       },
+};
+
 /* NOTE: sc7280 only has one DSC hard slice encoder */
 static const struct dpu_dsc_cfg sc7280_dsc[] = {
        {
@@ -247,6 +255,8 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
        .mixer = sc7280_lm,
        .pingpong_count = ARRAY_SIZE(sc7280_pp),
        .pingpong = sc7280_pp,
+       .merge_3d_count = ARRAY_SIZE(sc7280_merge_3d),
+       .merge_3d = sc7280_merge_3d,
        .dsc_count = ARRAY_SIZE(sc7280_dsc),
        .dsc = sc7280_dsc,
        .wb_count = ARRAY_SIZE(sc7280_wb),