/* These should not ever be either read or written, but we
initialise them anyway. */
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->guest_NRADDR = 0;
vex_state->guest_SC_CLASS = 0;
// /* */ ALWAYSDEFD(guest_GDT),
/* 10 */ ALWAYSDEFD(guest_EMNOTE),
/* 11 */ ALWAYSDEFD(guest_SSEROUND),
- /* 12 */ ALWAYSDEFD(guest_TISTART),
- /* 13 */ ALWAYSDEFD(guest_TILEN),
+ /* 12 */ ALWAYSDEFD(guest_CMSTART),
+ /* 13 */ ALWAYSDEFD(guest_CMLEN),
/* 14 */ ALWAYSDEFD(guest_SC_CLASS),
/* 15 */ ALWAYSDEFD(guest_IP_AT_SYSCALL)
}
#define OFFB_YMM16 offsetof(VexGuestAMD64State,guest_YMM16)
#define OFFB_EMNOTE offsetof(VexGuestAMD64State,guest_EMNOTE)
-#define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART)
-#define OFFB_TILEN offsetof(VexGuestAMD64State,guest_TILEN)
+#define OFFB_CMSTART offsetof(VexGuestAMD64State,guest_CMSTART)
+#define OFFB_CMLEN offsetof(VexGuestAMD64State,guest_CMLEN)
#define OFFB_NRADDR offsetof(VexGuestAMD64State,guest_NRADDR)
/* Round addr down to the start of the containing block. */
stmt( IRStmt_Put(
- OFFB_TISTART,
+ OFFB_CMSTART,
binop( Iop_And64,
mkexpr(addr),
mkU64( ~(lineszB-1) ))) );
- stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
+ stmt( IRStmt_Put(OFFB_CMLEN, mkU64(lineszB) ) );
- jmp_lit(dres, Ijk_TInval, (Addr64)(guest_RIP_bbstart+delta));
+ jmp_lit(dres, Ijk_InvalICache, (Addr64)(guest_RIP_bbstart+delta));
DIP("clflush %s\n", dis_buf);
goto decode_success;
// injecting here can change. In which case the translation has to
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_RIP_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(19)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkU64(guest_RIP_curr_instr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(19)));
delta += 19;
stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_bbstart + delta) ) );
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
goto decode_success;
}
/* We don't know what it is. */
//ZZ vex_state->guest_GEFLAG3 = 0;
//ZZ
//ZZ vex_state->guest_EMNOTE = EmNote_NONE;
-//ZZ vex_state->guest_TISTART = 0;
-//ZZ vex_state->guest_TILEN = 0;
+//ZZ vex_state->guest_CMSTART = 0;
+//ZZ vex_state->guest_CMLEN = 0;
//ZZ vex_state->guest_NRADDR = 0;
//ZZ vex_state->guest_IP_AT_SYSCALL = 0;
//ZZ
/* 1 */ ALWAYSDEFD(guest_CC_OP),
/* 2 */ ALWAYSDEFD(guest_CC_NDEP),
/* 3 */ ALWAYSDEFD(guest_EMNOTE),
- /* 4 */ ALWAYSDEFD(guest_TISTART),
- /* 5 */ ALWAYSDEFD(guest_TILEN),
+ /* 4 */ ALWAYSDEFD(guest_CMSTART),
+ /* 5 */ ALWAYSDEFD(guest_CMLEN),
/* 6 */ ALWAYSDEFD(guest_NRADDR),
/* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL),
/* 8 */ ALWAYSDEFD(guest_FPCR),
//ZZ #define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2)
//ZZ #define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3)
-#define OFFB_TISTART offsetof(VexGuestARM64State,guest_TISTART)
-#define OFFB_TILEN offsetof(VexGuestARM64State,guest_TILEN)
+#define OFFB_CMSTART offsetof(VexGuestARM64State,guest_CMSTART)
+#define OFFB_CMLEN offsetof(VexGuestARM64State,guest_CMLEN)
/* ---------------- Integer registers ---------------- */
mkU64(~(lineszB - 1))) );
/* Set the invalidation range, request exit-and-invalidate, with
continuation at the next instruction. */
- stmt(IRStmt_Put(OFFB_TISTART, mkexpr(addr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(lineszB)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkexpr(addr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(lineszB)));
/* be paranoid ... */
stmt( IRStmt_MBE(Imbe_Fence) );
putPC(mkU64( guest_PC_curr_instr + 4 ));
dres->whatNext = Dis_StopHere;
- dres->jk_StopHere = Ijk_TInval;
+ dres->jk_StopHere = Ijk_InvalICache;
DIP("ic ivau, %s\n", nameIReg64orZR(tt));
return True;
}
*/
if ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20) {
/* Exactly the same scheme as for IC IVAU, except we observe the
- dMinLine size, and request an Ijk_InvalData instead of
- Ijk_TInval. */
+ dMinLine size, and request an Ijk_FlushDCache instead of
+ Ijk_InvalICache. */
/* We will always be provided with a valid dMinLine value. */
vassert(archinfo->arm64_dMinLine_lg2_szB >= 2
&& archinfo->arm64_dMinLine_lg2_szB <= 17);
mkU64(~(lineszB - 1))) );
/* Set the flush range, request exit-and-flush, with
continuation at the next instruction. */
- stmt(IRStmt_Put(OFFB_TISTART, mkexpr(addr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(lineszB)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkexpr(addr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(lineszB)));
/* be paranoid ... */
stmt( IRStmt_MBE(Imbe_Fence) );
putPC(mkU64( guest_PC_curr_instr + 4 ));
// injecting here can change. In which case the translation has to
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_PC_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(20)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkU64(guest_PC_curr_instr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(20)));
putPC(mkU64( guest_PC_curr_instr + 20 ));
dres->whatNext = Dis_StopHere;
- dres->jk_StopHere = Ijk_TInval;
+ dres->jk_StopHere = Ijk_InvalICache;
return True;
}
/* We don't know what it is. */
vex_state->guest_GEFLAG3 = 0;
vex_state->guest_EMNOTE = EmNote_NONE;
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->guest_NRADDR = 0;
vex_state->guest_IP_AT_SYSCALL = 0;
/* 1 */ ALWAYSDEFD(guest_CC_OP),
/* 2 */ ALWAYSDEFD(guest_CC_NDEP),
/* 3 */ ALWAYSDEFD(guest_EMNOTE),
- /* 4 */ ALWAYSDEFD(guest_TISTART),
- /* 5 */ ALWAYSDEFD(guest_TILEN),
+ /* 4 */ ALWAYSDEFD(guest_CMSTART),
+ /* 5 */ ALWAYSDEFD(guest_CMLEN),
/* 6 */ ALWAYSDEFD(guest_NRADDR),
/* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL),
/* 8 */ ALWAYSDEFD(guest_TPIDRURO),
#define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2)
#define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3)
-#define OFFB_TISTART offsetof(VexGuestARMState,guest_TISTART)
-#define OFFB_TILEN offsetof(VexGuestARMState,guest_TILEN)
+#define OFFB_CMSTART offsetof(VexGuestARMState,guest_CMSTART)
+#define OFFB_CMLEN offsetof(VexGuestARMState,guest_CMLEN)
/* ---------------- Integer registers ---------------- */
// injecting here can change. In which case the translation has to
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_R15_curr_instr_notENC)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU32(20)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_R15_curr_instr_notENC)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(20)));
llPutIReg(15, mkU32( guest_R15_curr_instr_notENC + 20 ));
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
goto decode_success;
}
/* We don't know what it is. Set opc1/opc2 so decode_failure
// injecting here can change. In which case the translation has to
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_R15_curr_instr_notENC)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU32(20)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_R15_curr_instr_notENC)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(20)));
llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 ));
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
goto decode_success;
}
/* We don't know what it is. Set insn0 so decode_failure
not to disassemble any instructions into it; this is indicated
by the callback returning True.
- offB_TIADDR and offB_TILEN are the offsets of guest_TIADDR and
- guest_TILEN. Since this routine has to work for any guest state,
+ offB_CMADDR and offB_CMLEN are the offsets of guest_CMADDR and
+ guest_CMLEN. Since this routine has to work for any guest state,
without knowing what it is, those offsets have to passed in.
callback_opaque is a caller-supplied pointer to data which the
/*IN*/ IRType guest_word_type,
/*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*),
/*IN*/ Bool (*preamble_function)(void*,IRSB*),
- /*IN*/ Int offB_GUEST_TISTART,
- /*IN*/ Int offB_GUEST_TILEN,
+ /*IN*/ Int offB_GUEST_CMSTART,
+ /*IN*/ Int offB_GUEST_CMLEN,
/*IN*/ Int offB_GUEST_IP,
/*IN*/ Int szB_GUEST_IP
)
vassert(!nm_spec);
}
- /* Set TISTART and TILEN. These will describe to the despatcher
+ /* Set CMSTART and CMLEN. These will describe to the despatcher
the area of guest code to invalidate should we exit with a
self-check failure. */
= IRStmt_WrTmp(tilen_tmp, IRExpr_Const(len2check_IRConst) );
irsb->stmts[selfcheck_idx + i * 5 + 2]
- = IRStmt_Put( offB_GUEST_TISTART, IRExpr_RdTmp(tistart_tmp) );
+ = IRStmt_Put( offB_GUEST_CMSTART, IRExpr_RdTmp(tistart_tmp) );
irsb->stmts[selfcheck_idx + i * 5 + 3]
- = IRStmt_Put( offB_GUEST_TILEN, IRExpr_RdTmp(tilen_tmp) );
+ = IRStmt_Put( offB_GUEST_CMLEN, IRExpr_RdTmp(tilen_tmp) );
/* Generate the entry point descriptors */
if (abiinfo_both->host_ppc_calls_use_fndescrs) {
? IRExpr_Const(IRConst_U64(expectedhW))
: IRExpr_Const(IRConst_U32(expectedhW))
),
- Ijk_TInval,
+ Ijk_InvalICache,
/* Where we must restart if there's a failure: at the
first extent, regardless of which extent the
failure actually happened in. */
/*IN*/ IRType guest_word_type,
/*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*),
/*IN*/ Bool (*preamble_function)(void*,IRSB*),
- /*IN*/ Int offB_GUEST_TISTART,
- /*IN*/ Int offB_GUEST_TILEN,
+ /*IN*/ Int offB_GUEST_CMSTART,
+ /*IN*/ Int offB_GUEST_CMLEN,
/*IN*/ Int offB_GUEST_IP,
/*IN*/ Int szB_GUEST_IP
);
vex_state->guest_EMNOTE = 0;
/* For clflush: record start and length of area to invalidate */
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->host_EvC_COUNTER = 0;
vex_state->host_EvC_FAILADDR = 0;
vex_state->guest_EMNOTE = 0;
/* For clflush: record start and length of area to invalidate */
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->host_EvC_COUNTER = 0;
vex_state->host_EvC_FAILADDR = 0;
/* 0 */ ALWAYSDEFD32(guest_r0),
/* 1 */ ALWAYSDEFD32(guest_r1),
/* 2 */ ALWAYSDEFD32(guest_EMNOTE),
- /* 3 */ ALWAYSDEFD32(guest_TISTART),
- /* 4 */ ALWAYSDEFD32(guest_TILEN),
+ /* 3 */ ALWAYSDEFD32(guest_CMSTART),
+ /* 4 */ ALWAYSDEFD32(guest_CMLEN),
/* 5 */ ALWAYSDEFD32(guest_r29),
/* 6 */ ALWAYSDEFD32(guest_r31),
/* 7 */ ALWAYSDEFD32(guest_ULR)
.alwaysDefd = {
/* 0 */ ALWAYSDEFD64 (guest_r0),
/* 1 */ ALWAYSDEFD64 (guest_EMNOTE),
- /* 2 */ ALWAYSDEFD64 (guest_TISTART),
- /* 3 */ ALWAYSDEFD64 (guest_TILEN),
+ /* 2 */ ALWAYSDEFD64 (guest_CMSTART),
+ /* 3 */ ALWAYSDEFD64 (guest_CMLEN),
/* 4 */ ALWAYSDEFD64 (guest_r29),
/* 5 */ ALWAYSDEFD64 (guest_r31),
/* 6 */ ALWAYSDEFD64 (guest_ULR)
vex_inject_ir(irsb, Iend_BE);
#endif
if (mode64) {
- stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_TISTART),
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_CMSTART),
mkU64(guest_PC_curr_instr)));
- stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_TILEN),
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_CMLEN),
mkU64(20)));
putPC(mkU64(guest_PC_curr_instr + 20));
} else {
- stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_TISTART),
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMSTART),
mkU32(guest_PC_curr_instr)));
- stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_TILEN),
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMLEN),
mkU32(20)));
putPC(mkU32(guest_PC_curr_instr + 20));
}
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
dres.len = 20;
delta += 20;
goto decode_success;
vex_state->guest_EMNOTE = EmNote_NONE;
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->guest_NRADDR = 0;
vex_state->guest_NRADDR_GPR2 = 0;
vex_state->padding = 0;
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->guest_NRADDR = 0;
vex_state->guest_NRADDR_GPR2 = 0;
.alwaysDefd
= { /* 0 */ ALWAYSDEFD32(guest_CIA),
/* 1 */ ALWAYSDEFD32(guest_EMNOTE),
- /* 2 */ ALWAYSDEFD32(guest_TISTART),
- /* 3 */ ALWAYSDEFD32(guest_TILEN),
+ /* 2 */ ALWAYSDEFD32(guest_CMSTART),
+ /* 3 */ ALWAYSDEFD32(guest_CMLEN),
/* 4 */ ALWAYSDEFD32(guest_VSCR),
/* 5 */ ALWAYSDEFD32(guest_FPROUND),
/* 6 */ ALWAYSDEFD32(guest_NRADDR),
.alwaysDefd
= { /* 0 */ ALWAYSDEFD64(guest_CIA),
/* 1 */ ALWAYSDEFD64(guest_EMNOTE),
- /* 2 */ ALWAYSDEFD64(guest_TISTART),
- /* 3 */ ALWAYSDEFD64(guest_TILEN),
+ /* 2 */ ALWAYSDEFD64(guest_CMSTART),
+ /* 3 */ ALWAYSDEFD64(guest_CMLEN),
/* 4 */ ALWAYSDEFD64(guest_VSCR),
/* 5 */ ALWAYSDEFD64(guest_FPROUND),
/* 6 */ ALWAYSDEFD64(guest_NRADDR),
#define OFFB_VRSAVE offsetofPPCGuestState(guest_VRSAVE)
#define OFFB_VSCR offsetofPPCGuestState(guest_VSCR)
#define OFFB_EMNOTE offsetofPPCGuestState(guest_EMNOTE)
-#define OFFB_TISTART offsetofPPCGuestState(guest_TISTART)
-#define OFFB_TILEN offsetofPPCGuestState(guest_TILEN)
+#define OFFB_CMSTART offsetofPPCGuestState(guest_CMSTART)
+#define OFFB_CMLEN offsetofPPCGuestState(guest_CMLEN)
#define OFFB_NRADDR offsetofPPCGuestState(guest_NRADDR)
#define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2)
#define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR)
PPC_GST_VRSAVE, // Vector Save/Restore Register
PPC_GST_VSCR, // Vector Status and Control Register
PPC_GST_EMWARN, // Emulation warnings
- PPC_GST_TISTART,// For icbi: start of area to invalidate
- PPC_GST_TILEN, // For icbi: length of area to invalidate
+ PPC_GST_CMSTART,// For icbi: start of area to invalidate
+ PPC_GST_CMLEN, // For icbi: length of area to invalidate
PPC_GST_IP_AT_SYSCALL, // the CIA of the most recently executed SC insn
PPC_GST_SPRG3_RO, // SPRG3
PPC_GST_TFHAR, // Transactional Failure Handler Address Register
stmt( IRStmt_Put( OFFB_EMNOTE,src) );
break;
- case PPC_GST_TISTART:
+ case PPC_GST_CMSTART:
vassert( ty_src == ty );
- stmt( IRStmt_Put( OFFB_TISTART, src) );
+ stmt( IRStmt_Put( OFFB_CMSTART, src) );
break;
- case PPC_GST_TILEN:
+ case PPC_GST_CMLEN:
vassert( ty_src == ty );
- stmt( IRStmt_Put( OFFB_TILEN, src) );
+ stmt( IRStmt_Put( OFFB_CMLEN, src) );
break;
case PPC_GST_TEXASR:
assign( addr, binop( mkSzOp(ty, Iop_And8),
mkexpr(EA),
mkSzImm(ty, ~(((ULong)lineszB)-1) )) );
- putGST( PPC_GST_TISTART, mkexpr(addr) );
- putGST( PPC_GST_TILEN, mkSzImm(ty, lineszB) );
+ putGST( PPC_GST_CMSTART, mkexpr(addr) );
+ putGST( PPC_GST_CMLEN, mkSzImm(ty, lineszB) );
/* be paranoid ... */
stmt( IRStmt_MBE(Imbe_Fence) );
putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr()));
- dres->jk_StopHere = Ijk_TInval;
+ dres->jk_StopHere = Ijk_InvalICache;
dres->whatNext = Dis_StopHere;
break;
}
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkSzImm(ty, guest_CIA_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkSzImm(ty, 20)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkSzImm(ty, guest_CIA_curr_instr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkSzImm(ty, 20)));
putGST( PPC_GST_CIA, mkSzImm( ty, guest_CIA_bbstart + delta ));
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
goto decode_success;
}
/* We don't know what it is. Set opc1/opc2 so decode_failure
/*------------------------------------------------------------*/
state->guest_NRADDR = 0;
- state->guest_TISTART = 0;
- state->guest_TILEN = 0;
+ state->guest_CMSTART = 0;
+ state->guest_CMLEN = 0;
state->guest_IP_AT_SYSCALL = 0;
state->guest_EMNOTE = EmNote_NONE;
state->host_EvC_COUNTER = 0;
/* 0 */ ALWAYSDEFD(guest_CC_OP), /* generic */
/* 1 */ ALWAYSDEFD(guest_CC_NDEP), /* generic */
/* 2 */ ALWAYSDEFD(guest_EMNOTE), /* generic */
- /* 3 */ ALWAYSDEFD(guest_TISTART), /* generic */
- /* 4 */ ALWAYSDEFD(guest_TILEN), /* generic */
+ /* 3 */ ALWAYSDEFD(guest_CMSTART), /* generic */
+ /* 4 */ ALWAYSDEFD(guest_CMLEN), /* generic */
/* 5 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), /* generic */
/* 6 */ ALWAYSDEFD(guest_IA), /* control reg */
/* 7 */ ALWAYSDEFD(guest_fpc), /* control reg */
{
vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
- stmt(IRStmt_Exit(condition, Ijk_TInval, IRConst_U64(guest_IA_curr_instr),
+ stmt(IRStmt_Exit(condition, Ijk_InvalICache,
+ IRConst_U64(guest_IA_curr_instr),
S390X_GUEST_OFFSET(guest_IA)));
}
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART),
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART),
mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4)));
restart_if(mkexpr(cond));
ss.bytes = last_execute_target;
mkIRExprVec_1(load(Ity_I64, mkexpr(addr2))));
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART),
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART),
mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4)));
restart_if(IRExpr_Const(IRConst_U1(True)));
/* we know that this will be invalidated */
put_IA(mkaddr_expr(guest_IA_next_instr));
dis_res->whatNext = Dis_StopHere;
- dis_res->jk_StopHere = Ijk_TInval;
+ dis_res->jk_StopHere = Ijk_InvalICache;
break;
}
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART), mkU64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4)));
restart_if(mkexpr(cond));
/* Now comes the actual translation */
injecting here can change. In which case the translation has to
be redone. For ease of handling, we simply invalidate all the
time. */
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART),
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART),
mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN),
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN),
mkU64(guest_IA_next_instr - guest_IA_curr_instr)));
vassert(guest_IA_next_instr - guest_IA_curr_instr ==
S390_SPECIAL_OP_PREAMBLE_SIZE + S390_SPECIAL_OP_SIZE);
put_IA(mkaddr_expr(guest_IA_next_instr));
dis_res->whatNext = Dis_StopHere;
- dis_res->jk_StopHere = Ijk_TInval;
+ dis_res->jk_StopHere = Ijk_InvalICache;
} else {
/* We don't know what it is. */
return S390_DECODE_UNKNOWN_SPECIAL_INSN;
vex_state->guest_EMNOTE = EmNote_NONE;
/* SSE2 has a 'clflush' cache-line-invalidator which uses these. */
- vex_state->guest_TISTART = 0;
- vex_state->guest_TILEN = 0;
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
vex_state->guest_NRADDR = 0;
vex_state->guest_SC_CLASS = 0;
/* 17 */ ALWAYSDEFD(guest_GDT),
/* 18 */ ALWAYSDEFD(guest_EMNOTE),
/* 19 */ ALWAYSDEFD(guest_SSEROUND),
- /* 20 */ ALWAYSDEFD(guest_TISTART),
- /* 21 */ ALWAYSDEFD(guest_TILEN),
+ /* 20 */ ALWAYSDEFD(guest_CMSTART),
+ /* 21 */ ALWAYSDEFD(guest_CMLEN),
/* 22 */ ALWAYSDEFD(guest_SC_CLASS),
/* 23 */ ALWAYSDEFD(guest_IP_AT_SYSCALL)
}
#define OFFB_EMNOTE offsetof(VexGuestX86State,guest_EMNOTE)
-#define OFFB_TISTART offsetof(VexGuestX86State,guest_TISTART)
-#define OFFB_TILEN offsetof(VexGuestX86State,guest_TILEN)
+#define OFFB_CMSTART offsetof(VexGuestX86State,guest_CMSTART)
+#define OFFB_CMLEN offsetof(VexGuestX86State,guest_CMLEN)
#define OFFB_NRADDR offsetof(VexGuestX86State,guest_NRADDR)
#define OFFB_IP_AT_SYSCALL offsetof(VexGuestX86State,guest_IP_AT_SYSCALL)
// injecting here can change. In which case the translation has to
// be redone. For ease of handling, we simply invalidate all the
// time.
- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_EIP_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU32(14)));
+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_EIP_curr_instr)));
+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(14)));
delta += 14;
stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_bbstart + delta) ) );
dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = Ijk_TInval;
+ dres.jk_StopHere = Ijk_InvalICache;
goto decode_success;
}
/* We don't know what it is. */
/* Round addr down to the start of the containing block. */
stmt( IRStmt_Put(
- OFFB_TISTART,
+ OFFB_CMSTART,
binop( Iop_And32,
mkexpr(addr),
mkU32( ~(lineszB-1) ))) );
- stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) );
+ stmt( IRStmt_Put(OFFB_CMLEN, mkU32(lineszB) ) );
- jmp_lit(&dres, Ijk_TInval, (Addr32)(guest_EIP_bbstart+delta));
+ jmp_lit(&dres, Ijk_InvalICache, (Addr32)(guest_EIP_bbstart+delta));
DIP("clflush %s\n", dis_buf);
goto decode_success;
case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_SigSEGV:
case Ijk_SigTRAP:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield:
{
HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
case Ijk_SigSEGV:
case Ijk_SigTRAP:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield: {
HReg r = iselIntExpr_R(env, next);
AMD64AMode* amRIP = AMD64AMode_IR(offsIP, hregAMD64_RBP());
//case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
//case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_FlushDCache: trcval = VEX_TRC_JMP_FLUSHDCACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
//case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
//ZZ case Ijk_NoDecode:
//ZZ case Ijk_NoRedir:
//ZZ case Ijk_Sys_syscall:
-//ZZ case Ijk_TInval:
+//ZZ case Ijk_InvalICache:
//ZZ case Ijk_Yield:
//ZZ {
//ZZ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
case Ijk_NoDecode:
case Ijk_NoRedir:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_FlushDCache:
//ZZ case Ijk_Yield:
{
//case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
//case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
//case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
//case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_NoDecode:
case Ijk_NoRedir:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield:
{
HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
case Ijk_NoDecode:
case Ijk_NoRedir:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield:
{
HReg r = iselIntExpr_R(env, next);
case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
/* case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; */
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
case Ijk_SigILL: trcval = VEX_TRC_JMP_SIGILL; break;
case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
case Ijk_SigFPE_IntDiv:
case Ijk_SigFPE_IntOvf:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
{
HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
addInstr(env, MIPSInstr_XAssisted(r, amPC, cc,
case Ijk_SigFPE_IntDiv:
case Ijk_SigFPE_IntOvf:
case Ijk_Sys_syscall:
- case Ijk_TInval: {
+ case Ijk_InvalICache: {
HReg r = iselWordExpr_R(env, next);
MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL, jk));
case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
//case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
//case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_SigBUS:
case Ijk_SigTRAP:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
{
HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
addInstr(env, PPCInstr_XAssisted(r, amCIA, cc,
case Ijk_SigBUS:
case Ijk_SigTRAP:
case Ijk_Sys_syscall:
- case Ijk_TInval:
+ case Ijk_InvalICache:
{
HReg r = iselWordExpr_R(env, next);
PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
case Ijk_EmFail: return "EmFail";
case Ijk_NoDecode: return "NoDecode";
case Ijk_MapFail: return "MapFail";
- case Ijk_TInval: return "Invalidate";
+ case Ijk_InvalICache: return "Invalidate";
case Ijk_NoRedir: return "NoRedir";
case Ijk_SigTRAP: return "SigTRAP";
case Ijk_SigSEGV: return "SigSEGV";
case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_EmFail:
case Ijk_EmWarn:
case Ijk_NoDecode:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Sys_syscall:
case Ijk_ClientReq:
case Ijk_NoRedir:
case Ijk_EmFail:
case Ijk_EmWarn:
case Ijk_NoDecode:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Sys_syscall:
case Ijk_ClientReq:
case Ijk_NoRedir:
case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_Sys_int130:
case Ijk_Sys_syscall:
case Ijk_Sys_sysenter:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield:
{
HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
case Ijk_Sys_int130:
case Ijk_Sys_syscall:
case Ijk_Sys_sysenter:
- case Ijk_TInval:
+ case Ijk_InvalICache:
case Ijk_Yield:
{
HReg r = iselIntExpr_R(env, next);
case Ijk_EmFail: vex_printf("EmFail"); break;
case Ijk_NoDecode: vex_printf("NoDecode"); break;
case Ijk_MapFail: vex_printf("MapFail"); break;
- case Ijk_TInval: vex_printf("Invalidate"); break;
+ case Ijk_InvalICache: vex_printf("InvalICache"); break;
case Ijk_FlushDCache: vex_printf("FlushDCache"); break;
case Ijk_NoRedir: vex_printf("NoRedir"); break;
case Ijk_SigILL: vex_printf("SigILL"); break;
HInstrArray* vcode;
HInstrArray* rcode;
Int i, j, k, out_used, guest_sizeB;
- Int offB_TISTART, offB_TILEN, offB_GUEST_IP, szB_GUEST_IP;
+ Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP;
Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR;
UChar insn_bytes[128];
IRType guest_word_type;
disInstrFn = NULL;
guest_word_type = Ity_INVALID;
host_word_type = Ity_INVALID;
- offB_TISTART = 0;
- offB_TILEN = 0;
+ offB_CMSTART = 0;
+ offB_CMLEN = 0;
offB_GUEST_IP = 0;
szB_GUEST_IP = 0;
offB_HOST_EvC_COUNTER = 0;
guest_sizeB = sizeof(VexGuestX86State);
guest_word_type = Ity_I32;
guest_layout = &x86guest_layout;
- offB_TISTART = offsetof(VexGuestX86State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestX86State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP);
szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP );
offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestX86State) % 16);
- vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4);
- vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4);
+ vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4);
vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4);
break;
guest_sizeB = sizeof(VexGuestAMD64State);
guest_word_type = Ity_I64;
guest_layout = &amd64guest_layout;
- offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP);
szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP );
offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestAMD64State) % 16);
- vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8);
- vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8);
+ vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8);
+ vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8);
break;
guest_sizeB = sizeof(VexGuestPPC32State);
guest_word_type = Ity_I32;
guest_layout = &ppc32Guest_layout;
- offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA);
szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA );
offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestPPC32State) % 16);
- vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4);
- vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4);
+ vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4);
vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4);
break;
guest_sizeB = sizeof(VexGuestPPC64State);
guest_word_type = Ity_I64;
guest_layout = &ppc64Guest_layout;
- offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA);
szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA );
offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestPPC64State) % 16);
- vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8);
- vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8);
+ vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8);
+ vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8);
vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8);
break;
guest_sizeB = sizeof(VexGuestS390XState);
guest_word_type = Ity_I64;
guest_layout = &s390xGuest_layout;
- offB_TISTART = offsetof(VexGuestS390XState,guest_TISTART);
- offB_TILEN = offsetof(VexGuestS390XState,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA);
szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA);
offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestS390XState) % 16);
- vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8);
- vassert(sizeof( ((VexGuestS390XState*)0)->guest_TILEN ) == 8);
+ vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8);
+ vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8);
break;
guest_sizeB = sizeof(VexGuestARMState);
guest_word_type = Ity_I32;
guest_layout = &armGuest_layout;
- offB_TISTART = offsetof(VexGuestARMState,guest_TISTART);
- offB_TILEN = offsetof(VexGuestARMState,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T);
szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T );
offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestARMState) % 16);
- vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4);
- vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4);
+ vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4);
vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4);
break;
guest_sizeB = sizeof(VexGuestARM64State);
guest_word_type = Ity_I64;
guest_layout = &arm64Guest_layout;
- offB_TISTART = offsetof(VexGuestARM64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestARM64State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC);
szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC );
offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestARM64State) % 16);
- vassert(sizeof( ((VexGuestARM64State*)0)->guest_TISTART) == 8);
- vassert(sizeof( ((VexGuestARM64State*)0)->guest_TILEN ) == 8);
+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8);
+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8);
break;
guest_sizeB = sizeof(VexGuestMIPS32State);
guest_word_type = Ity_I32;
guest_layout = &mips32Guest_layout;
- offB_TISTART = offsetof(VexGuestMIPS32State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestMIPS32State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC);
szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC );
offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestMIPS32State) % 16);
- vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4);
- vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4);
vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4);
break;
guest_sizeB = sizeof(VexGuestMIPS64State);
guest_word_type = Ity_I64;
guest_layout = &mips64Guest_layout;
- offB_TISTART = offsetof(VexGuestMIPS64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestMIPS64State,guest_TILEN);
+ offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN);
offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC);
szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC );
offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER);
offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestMIPS64State) % 16);
- vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TISTART) == 8);
- vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TILEN ) == 8);
+ vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8);
+ vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8);
break;
guest_word_type,
vta->needs_self_check,
vta->preamble_function,
- offB_TISTART,
- offB_TILEN,
+ offB_CMSTART,
+ offB_CMLEN,
offB_GUEST_IP,
szB_GUEST_IP );
ALL GUEST ARCHITECTURES
~~~~~~~~~~~~~~~~~~~~~~~
- The guest state must contain two pseudo-registers, guest_TISTART
- and guest_TILEN. These are used to pass the address of areas of
- guest code, translations of which are to be invalidated, back to
- the despatcher. Both pseudo-regs must have size equal to the guest
- word size.
+ The guest state must contain two pseudo-registers, guest_CMSTART
+ and guest_CMLEN. These are used to specify guest address ranges,
+ either of code to be invalidated, when used in conjunction with
+ Ijk_InvalICache, or of d-cache ranges to be flushed, when used in
+ conjunction with Ijk_FlushDCache. In such cases, the two _CM
+ pseudo-regs should be filled in by the IR, and then an exit with
+ one of the two abovementioned Ijk_ kinds should happen, so that the
+ dispatcher can action them. Both pseudo-regs must have size equal
+ to the guest word size.
The architecture must a third pseudo-register, guest_NRADDR, also
guest-word-sized. This is used to record the unredirected guest
compilation breakage. On amd64, these two fields are set to
zero by LibVEX_GuestAMD64_initialise and then should be
ignored forever thereafter. */
- ULong guest_TISTART;
- ULong guest_TILEN;
+ ULong guest_CMSTART;
+ ULong guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* Emulation notes */
UInt guest_EMNOTE;
- /* For clflush: record start and length of area to invalidate */
- UInt guest_TISTART;
- UInt guest_TILEN;
+ /* For clinval/clflush: record start and length of area */
+ UInt guest_CMSTART;
+ UInt guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* Emulation notes */
UInt guest_EMNOTE;
- /* For clflush: record start and length of area to invalidate */
- ULong guest_TISTART;
- ULong guest_TILEN;
+ /* For clflush/clinval: record start and length of area */
+ ULong guest_CMSTART;
+ ULong guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* 424 */ UInt guest_EMNOTE;
/* For clflush: record start and length of area to invalidate */
- /* 428 */ UInt guest_TISTART;
- /* 432 */ UInt guest_TILEN;
+ /* 428 */ UInt guest_CMSTART;
+ /* 432 */ UInt guest_CMLEN;
/* 436 */ UInt guest_NRADDR;
/* 440 */ UInt host_EvC_FAILADDR;
UInt guest_EMNOTE; /* 568 */
/* For clflush: record start and length of area to invalidate */
- ULong guest_TISTART; /* 576 */
- ULong guest_TILEN; /* 584 */
+ ULong guest_CMSTART; /* 576 */
+ ULong guest_CMLEN; /* 584 */
ULong guest_NRADDR; /* 592 */
/* 1196 */ UInt guest_EMNOTE;
/* For icbi: record start and length of area to invalidate */
- /* 1200 */ UInt guest_TISTART;
- /* 1204 */ UInt guest_TILEN;
+ /* 1200 */ UInt guest_CMSTART;
+ /* 1204 */ UInt guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* 1340 */ UInt padding;
/* For icbi: record start and length of area to invalidate */
- /* 1344 */ ULong guest_TISTART;
- /* 1352 */ ULong guest_TILEN;
+ /* 1344 */ ULong guest_CMSTART;
+ /* 1352 */ ULong guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* See comments at bottom of libvex.h */
/* 384 */ ULong guest_NRADDR;
- /* 392 */ ULong guest_TISTART;
- /* 400 */ ULong guest_TILEN;
+ /* 392 */ ULong guest_CMSTART;
+ /* 400 */ ULong guest_CMLEN;
/* Used when backing up to restart a syscall that has
been interrupted by a signal. See also comment in
/* Emulation notes */
UInt guest_EMNOTE;
- /* For clflush: record start and length of area to invalidate */
- UInt guest_TISTART;
- UInt guest_TILEN;
+ /* For clflush/clinval: record start and length of area */
+ UInt guest_CMSTART;
+ UInt guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
/* This describes hints which can be passed to the dispatcher at guest
control-flow transfer points.
- Re Ijk_TInval: the guest state _must_ have two pseudo-registers,
- guest_TISTART and guest_TILEN, which specify the start and length
- of the region to be invalidated. These are both the size of a
- guest word. It is the responsibility of the relevant toIR.c to
- ensure that these are filled in with suitable values before issuing
- a jump of kind Ijk_TInval.
-
- Ijk_TInval requests invalidation of translations taken from the
- requested range. Ijk_FlushDCache requests flushing of the D cache
- for the specified range.
+ Re Ijk_InvalICache and Ijk_FlushDCache: the guest state _must_ have
+ two pseudo-registers, guest_CMSTART and guest_CMLEN, which specify
+ the start and length of the region to be invalidated. CM stands
+ for "Cache Management". These are both the size of a guest word.
+ It is the responsibility of the relevant toIR.c to ensure that
+ these are filled in with suitable values before issuing a jump of
+ kind Ijk_InvalICache or Ijk_FlushDCache.
+
+ Ijk_InvalICache requests invalidation of translations taken from
+ the requested range. Ijk_FlushDCache requests flushing of the D
+ cache for the specified range.
Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a
pseudo-register guest_EMNOTE, which is 32-bits regardless of the
Ijk_EmFail, /* emulation critical (FATAL) error; give up */
Ijk_NoDecode, /* current instruction cannot be decoded */
Ijk_MapFail, /* Vex-provided address translation failed */
- Ijk_TInval, /* Inval icache to PoU in [TISTART, +TILEN) */
- Ijk_FlushDCache, /* Clean dcache to PoU in [TISTART, +TILEN) */
+ Ijk_InvalICache, /* Inval icache for range [CMSTART, +CMLEN) */
+ Ijk_FlushDCache, /* Flush dcache for range [CMSTART, +CMLEN) */
Ijk_NoRedir, /* Jump to un-redirected guest addr */
Ijk_SigILL, /* current instruction synths SIGILL */
Ijk_SigTRAP, /* current instruction synths SIGTRAP */
with Valgrind's VG_TRC_ values, which are 60 or below.
*/
-#define VEX_TRC_JMP_TINVAL 61 /* invalidate translations before
- continuing */
+#define VEX_TRC_JMP_INVALICACHE 61 /* invalidate icache (translations)
+ before continuing */
#define VEX_TRC_JMP_FLUSHDCACHE 103 /* flush dcache before continuing */
#define VEX_TRC_JMP_NOREDIR 81 /* jump to undirected guest addr */
projects / thirdparty / valgrind.git / commitdiff
