dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC.  The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 708ab6bd7d44860e1e72328e287d660248b85abe..bc2fd3761328c1dc4964d20d9925374e84cf0262 100644 (file)
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -53,6 +53,7 @@ properties:
       - renesas,r8a779g0-cpg-mssr # R-Car V4H
       - renesas,r8a779h0-cpg-mssr # R-Car V4M
       - renesas,r9a09g077-cpg-mssr # RZ/T2H
+      - renesas,r9a09g087-cpg-mssr # RZ/N2H
 
   reg:
     minItems: 1
@@ -112,7 +113,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g077-cpg-mssr
+            enum:
+              - renesas,r9a09g077-cpg-mssr
+              - renesas,r9a09g087-cpg-mssr
     then:
       properties:
         reg:

diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
new file mode 100644 (file)
index 0000000..f28166d
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G087 CPG Core Clocks */
+#define R9A09G087_CLK_CA55C0           0
+#define R9A09G087_CLK_CA55C1           1
+#define R9A09G087_CLK_CA55C2           2
+#define R9A09G087_CLK_CA55C3           3
+#define R9A09G087_CLK_CA55S            4
+#define R9A09G087_CLK_CR52_CPU0                5
+#define R9A09G087_CLK_CR52_CPU1                6
+#define R9A09G087_CLK_CKIO             7
+#define R9A09G087_CLK_PCLKAH           8
+#define R9A09G087_CLK_PCLKAM           9
+#define R9A09G087_CLK_PCLKAL           10
+#define R9A09G087_CLK_PCLKGPTL         11
+#define R9A09G087_CLK_PCLKH            12
+#define R9A09G087_CLK_PCLKM            13
+#define R9A09G087_CLK_PCLKL            14
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */