spi: spi-nxp-fspi: Add OCT-DTR mode support

[ Upstream commit 0f67557763accbdd56681f17ed5350735198c57b ]

Add OCT-DTR mode support in default, since flexspi do not supports
swapping bytes on a 16 bit boundary in OCT-DTR mode, so mark swap16
as false.

lx2160a do not support DQS, so add a quirk to disable DTR mode for this
platform.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-5-bb9fe2a01889@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Stable-dep-of: 40ad64ac25bb ("spi: nxp-fspi: Propagate fwnode in ACPI case as well")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 825b2a36377c24750a9625cf3568ede3a6ecfc15..6cdeee9c581bd07913974ee952bfa2a57442fa7a 100644 (file)
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -325,6 +325,8 @@
 
 /* Access flash memory using IP bus only */
 #define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+/* Disable DTR */
+#define FSPI_QUIRK_DISABLE_DTR BIT(1)
 
 struct nxp_fspi_devtype_data {
        unsigned int rxfifo;
@@ -339,7 +341,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
        .rxfifo = SZ_512,       /* (64  * 64 bits)  */
        .txfifo = SZ_1K,        /* (128 * 64 bits)  */
        .ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
-       .quirks = 0,
+       .quirks = FSPI_QUIRK_DISABLE_DTR,
        .lut_num = 32,
        .little_endian = true,  /* little-endian    */
 };
@@ -1157,6 +1159,13 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
 };
 
 static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
+       .dtr = true,
+       .swap16 = false,
+       .per_op_freq = true,
+};
+
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = {
+       .dtr = false,
        .per_op_freq = true,
 };
 
@@ -1245,7 +1254,12 @@ static int nxp_fspi_probe(struct platform_device *pdev)
        ctlr->bus_num = -1;
        ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
        ctlr->mem_ops = &nxp_fspi_mem_ops;
-       ctlr->mem_caps = &nxp_fspi_mem_caps;
+
+       if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
+               ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr;
+       else
+               ctlr->mem_caps = &nxp_fspi_mem_caps;
+
        ctlr->dev.of_node = np;
 
        return devm_spi_register_controller(&pdev->dev, ctlr);