drm/i915/lt_phy: Enable dpll framework for xe3plpd

xe3plpd platform is supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for xe3plpd platform and remove the redirections
to the legacy code paths for clock enable/disable as well as
state mismatch checks that are no longer needed.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312101415.2669387-1-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe024250d3508e614289c03e2b054c33ecca2c70..ebefa889bc8c5930cd31c463a5c537ed32bd3754 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5285,7 +5285,7 @@ void intel_ddi_init(struct intel_display *display,
        if (HAS_LT_PHY(display)) {
                encoder->enable_clock = intel_mtl_pll_enable_clock;
                encoder->disable_clock = intel_mtl_pll_disable_clock;
-               encoder->port_pll_type = intel_mtl_port_pll_type;
+               encoder->port_pll_type = icl_ddi_tc_port_pll_type;
                if (intel_encoder_is_tc(encoder))
                        encoder->get_config = mtl_ddi_tc_phy_get_config;
                else

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dfc28af1ef889de66eb4b3cb4145b4ddffce6e9e..10b6c6fcb03f693d85f26a0fabceff2afecdd274 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5063,23 +5063,6 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
               !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
-static void
-pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
-                               const struct intel_crtc *crtc,
-                               const char *name,
-                               const struct intel_lt_phy_pll_state *a,
-                               const struct intel_lt_phy_pll_state *b)
-{
-       char *chipname = "LTPHY";
-
-       pipe_config_mismatch(p, fastset, crtc, name, chipname);
-
-       drm_printf(p, "expected:\n");
-       intel_lt_phy_dump_hw_state(p, a);
-       drm_printf(p, "found:\n");
-       intel_lt_phy_dump_hw_state(p, b);
-}
-
 bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
                          const struct intel_crtc_state *pipe_config,
@@ -5194,16 +5177,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        } \
 } while (0)
 
-#define PIPE_CONF_CHECK_PLL_LT(name) do { \
-       if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
-                                              &pipe_config->name)) { \
-               pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
-                                               &current_config->name, \
-                                               &pipe_config->name); \
-               ret = false; \
-       } \
-} while (0)
-
 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
        PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
        PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5430,10 +5403,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        if (display->dpll.mgr || HAS_GMCH(display))
                PIPE_CONF_CHECK_PLL(dpll_hw_state);
 
-       /* FIXME convert MTL+ platforms over to dpll_mgr */
-       if (HAS_LT_PHY(display))
-               PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
-
        PIPE_CONF_CHECK_X(dsi_pll.ctrl);
        PIPE_CONF_CHECK_X(dsi_pll.div);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 421767dd83678309bb3828da053b0421cae541cd..f5d4f7146fbc6ac33968b79404e849bf26c854e6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4724,7 +4724,6 @@ static bool xe3plpd_compare_hw_state(const struct intel_dpll_hw_state *_a,
        return intel_lt_phy_pll_compare_hw_state(a, b);
 }
 
-__maybe_unused
 static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
        .dpll_info = xe3plpd_plls,
        .compute_dplls = xe3plpd_compute_dplls,
@@ -4750,9 +4749,11 @@ void intel_dpll_init(struct intel_display *display)
 
        mutex_init(&display->dpll.lock);
 
-       if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
-               /* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */
+       if (display->platform.dg2)
+               /* No shared DPLLs on DG2; port PLLs are part of the PHY */
                dpll_mgr = NULL;
+       else if (DISPLAY_VER(display) >= 35)
+               dpll_mgr = &xe3plpd_pll_mgr;
        else if (DISPLAY_VER(display) >= 14)
                dpll_mgr = &mtl_pll_mgr;
        else if (display->platform.alderlake_p)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 5bbbc618286191b0935d6e7e74ec4498bad2ab74..657ad5cb0eff92c72061c4e4b847cf278a9ffa68 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -11,6 +11,7 @@
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
 #include "intel_display.h"
+#include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_display_utils.h"
 #include "intel_dpll.h"