* Copyright (c) 2008, Jouni Malinen <j@w1.fi>
* Copyright (c) 2011, Javier Lopez <jlopex@gmail.com>
* Copyright (c) 2016 - 2017 Intel Deutschland GmbH
- * Copyright (C) 2018 - 2025 Intel Corporation
+ * Copyright (C) 2018 - 2026 Intel Corporation
*/
#ifndef __MAC80211_HWSIM_I_H
struct ieee80211_channel channels_s1g[HWSIM_NUM_S1G_CHANNELS_US];
struct ieee80211_rate rates[HWSIM_NUM_RATES];
struct ieee80211_iface_combination if_combination;
- struct ieee80211_iface_limit if_limits[4];
+ struct ieee80211_iface_limit if_limits[5];
int n_if_limits;
/* Storage space for channels, etc. */
struct mac80211_hwsim_phy_data *phy_data;
* Copyright (c) 2008, Jouni Malinen <j@w1.fi>
* Copyright (c) 2011, Javier Lopez <jlopex@gmail.com>
* Copyright (c) 2016 - 2017 Intel Deutschland GmbH
- * Copyright (C) 2018 - 2025 Intel Corporation
+ * Copyright (C) 2018 - 2026 Intel Corporation
*/
/*
spin_lock_init(&data->nan.state_lock);
}
+ if (param->iftypes & BIT(NL80211_IFTYPE_NAN_DATA)) {
+ data->if_limits[n_limits].max = 2;
+ data->if_limits[n_limits].types = BIT(NL80211_IFTYPE_NAN_DATA);
+ n_limits++;
+ }
+
data->if_combination.radar_detect_widths =
BIT(NL80211_CHAN_WIDTH_5) |
BIT(NL80211_CHAN_WIDTH_10) |