pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume

Include the SR (Slew Rate) register in the PM suspend/resume register
cache.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 1c6b115e65d8578ea24d07a366088b29ca63a4b9..f5f645ba92e02e395f8f51a976c2bbc289848e0c 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -322,6 +322,7 @@ struct rzg2l_pinctrl_pin_settings {
  * @pupd: PUPD registers cache
  * @ien: IEN registers cache
  * @smt: SMT registers cache
+ * @sr: SR registers cache
  * @sd_ch: SD_CH registers cache
  * @eth_poc: ET_POC registers cache
  * @oen: Output Enable register cache
@@ -336,6 +337,7 @@ struct rzg2l_pinctrl_reg_cache {
        u32     *ien[2];
        u32     *pupd[2];
        u32     *smt[2];
+       u32     *sr[2];
        u8      sd_ch[2];
        u8      eth_poc[2];
        u8      oen;
@@ -2760,6 +2762,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
                if (!cache->smt[i])
                        return -ENOMEM;
 
+               cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]),
+                                           GFP_KERNEL);
+               if (!cache->sr[i])
+                       return -ENOMEM;
+
                /* Allocate dedicated cache. */
                dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
                                                        sizeof(*dedicated_cache->iolh[i]),
@@ -2772,6 +2779,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
                                                       GFP_KERNEL);
                if (!dedicated_cache->ien[i])
                        return -ENOMEM;
+
+               dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
+                                                     sizeof(*dedicated_cache->sr[i]),
+                                                     GFP_KERNEL);
+               if (!dedicated_cache->sr[i])
+                       return -ENOMEM;
        }
 
        pctrl->cache = cache;
@@ -3003,7 +3016,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
        struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
 
        for (u32 port = 0; port < nports; port++) {
-               bool has_iolh, has_ien, has_pupd, has_smt;
+               bool has_iolh, has_ien, has_pupd, has_smt, has_sr;
                u32 off, caps;
                u8 pincnt;
                u64 cfg;
@@ -3024,6 +3037,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
                has_ien = !!(caps & PIN_CFG_IEN);
                has_pupd = !!(caps & PIN_CFG_PUPD);
                has_smt = !!(caps & PIN_CFG_SMT);
+               has_sr = !!(caps & PIN_CFG_SR);
 
                if (suspend)
                        RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
@@ -3075,6 +3089,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
                                                         cache->smt[1][port]);
                        }
                }
+
+               if (has_sr) {
+                       RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),
+                                                cache->sr[0][port]);
+                       if (pincnt >= 4) {
+                               RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4,
+                                                        cache->sr[1][port]);
+                       }
+               }
        }
 }
 
@@ -3089,7 +3112,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
         * port offset are close together.
         */
        for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
-               bool has_iolh, has_ien;
+               bool has_iolh, has_ien, has_sr;
                u32 off, next_off = 0;
                u64 cfg, next_cfg;
                u8 pincnt;
@@ -3110,6 +3133,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
                /* And apply them in a single shot. */
                has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
                has_ien = !!(caps & PIN_CFG_IEN);
+               has_sr = !!(caps & PIN_CFG_SR);
                pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
 
                if (has_iolh) {
@@ -3120,7 +3144,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
                        RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
                                                 cache->ien[0][i]);
                }
-
+               if (has_sr) {
+                       RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),
+                                                cache->sr[0][i]);
+               }
                if (pincnt >= 4) {
                        if (has_iolh) {
                                RZG2L_PCTRL_REG_ACCESS32(suspend,
@@ -3132,6 +3159,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
                                                         pctrl->base + IEN(off) + 4,
                                                         cache->ien[1][i]);
                        }
+                       if (has_sr) {
+                               RZG2L_PCTRL_REG_ACCESS32(suspend,
+                                                        pctrl->base + SR(off) + 4,
+                                                        cache->sr[1][i]);
+                       }
                }
                caps = 0;
        }