clk: renesas: r9a09g047: Add I2C clocks/resets

Add I2C{0..8} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index f5966c08de417094115423bd92a5dc6b48d457d7..536d922bed703139f081145c653ea30a737c27ab 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -25,11 +25,13 @@ enum clk_ids {
 
        /* PLL Clocks */
        CLK_PLLCM33,
+       CLK_PLLCLN,
        CLK_PLLDTY,
        CLK_PLLCA55,
 
        /* Internal Core Clocks */
        CLK_PLLCM33_DIV16,
+       CLK_PLLCLN_DIV16,
        CLK_PLLDTY_ACPU,
        CLK_PLLDTY_ACPU_DIV4,
 
@@ -62,12 +64,15 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 
        /* PLL Clocks */
        DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+       DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
        DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
 
        /* Internal Core Clocks */
        DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
 
+       DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
+
        DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
 
@@ -89,6 +94,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(3, BIT(5))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
+       DEF_MOD("riic_8_ckm",                   CLK_PLLCM33_DIV16, 9, 3, 4, 19,
+                                               BUS_MSTOP(3, BIT(13))),
+       DEF_MOD("riic_0_ckm",                   CLK_PLLCLN_DIV16, 9, 4, 4, 20,
+                                               BUS_MSTOP(1, BIT(1))),
+       DEF_MOD("riic_1_ckm",                   CLK_PLLCLN_DIV16, 9, 5, 4, 21,
+                                               BUS_MSTOP(1, BIT(2))),
+       DEF_MOD("riic_2_ckm",                   CLK_PLLCLN_DIV16, 9, 6, 4, 22,
+                                               BUS_MSTOP(1, BIT(3))),
+       DEF_MOD("riic_3_ckm",                   CLK_PLLCLN_DIV16, 9, 7, 4, 23,
+                                               BUS_MSTOP(1, BIT(4))),
+       DEF_MOD("riic_4_ckm",                   CLK_PLLCLN_DIV16, 9, 8, 4, 24,
+                                               BUS_MSTOP(1, BIT(5))),
+       DEF_MOD("riic_5_ckm",                   CLK_PLLCLN_DIV16, 9, 9, 4, 25,
+                                               BUS_MSTOP(1, BIT(6))),
+       DEF_MOD("riic_6_ckm",                   CLK_PLLCLN_DIV16, 9, 10, 4, 26,
+                                               BUS_MSTOP(1, BIT(7))),
+       DEF_MOD("riic_7_ckm",                   CLK_PLLCLN_DIV16, 9, 11, 4, 27,
+                                               BUS_MSTOP(1, BIT(8))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -96,6 +119,15 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
        DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+       DEF_RST(9, 8, 4, 9),            /* RIIC_0_MRST */
+       DEF_RST(9, 9, 4, 10),           /* RIIC_1_MRST */
+       DEF_RST(9, 10, 4, 11),          /* RIIC_2_MRST */
+       DEF_RST(9, 11, 4, 12),          /* RIIC_3_MRST */
+       DEF_RST(9, 12, 4, 13),          /* RIIC_4_MRST */
+       DEF_RST(9, 13, 4, 14),          /* RIIC_5_MRST */
+       DEF_RST(9, 14, 4, 15),          /* RIIC_6_MRST */
+       DEF_RST(9, 15, 4, 16),          /* RIIC_7_MRST */
+       DEF_RST(10, 0, 4, 17),          /* RIIC_8_MRST */
 };
 
 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {