dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index f6e5f62b07c4a722c26da01ce1cf0071d156521b..7ecc4f0b235aac301a3bdd24563e3d83b6b1d698 100644 (file)
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -24,5 +24,6 @@
 #define R9A09G077_CLK_PCLKH            12
 #define R9A09G077_CLK_PCLKM            13
 #define R9A09G077_CLK_PCLKL            14
+#define R9A09G077_SDHI_CLKHS           15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index f28166d6015f479ed48ca68208f56350bd1aa917..925e57703925ddc8152147cb74da9478b7ace585 100644 (file)
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -24,5 +24,6 @@
 #define R9A09G087_CLK_PCLKH            12
 #define R9A09G087_CLK_PCLKM            13
 #define R9A09G087_CLK_PCLKL            14
+#define R9A09G087_SDHI_CLKHS           15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */