}
fn is_int_active(&self) -> bool {
- self.get_state().is_timer_int_active(self.index.into())
+ self.get_state()
+ .regs
+ .borrow()
+ .is_timer_int_active(self.index.into())
}
/// calculate next value of the general counter that matches the
}
fn get_int_route(&self) -> usize {
- if self.index <= 1 && self.get_state().is_legacy_mode() {
+ if self.index <= 1 && self.get_state().regs.borrow().is_legacy_mode() {
// If LegacyReplacement Route bit is set, HPET specification requires
// timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
// timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
fn set_irq(&self, set: bool) {
let route = self.get_int_route();
- if set && self.regs.is_int_enabled() && self.get_state().is_hpet_enabled() {
+ if set && self.regs.is_int_enabled() && self.get_state().regs.borrow().is_hpet_enabled() {
if self.regs.is_fsb_route_enabled() {
// SAFETY:
// the parameters are valid.
self.period = u64::from(self.period as u32); // truncate!
}
- if self.get_state().is_hpet_enabled() {
+ if self.get_state().regs.borrow().is_hpet_enabled() {
self.set_timer();
}
}
}
self.regs.clear_valset();
- if self.get_state().is_hpet_enabled() {
+ if self.get_state().regs.borrow().is_hpet_enabled() {
self.set_timer();
}
}
counter: u64,
}
+impl HPETRegisters {
+ fn is_legacy_mode(&self) -> bool {
+ self.config & (1 << HPET_CFG_LEG_RT_SHIFT) != 0
+ }
+
+ fn is_hpet_enabled(&self) -> bool {
+ self.config & (1 << HPET_CFG_ENABLE_SHIFT) != 0
+ }
+
+ fn is_timer_int_active(&self, index: usize) -> bool {
+ self.int_status & (1 << index) != 0
+ }
+}
+
/// HPET Event Timer Block Abstraction
#[repr(C)]
#[derive(qom::Object, hwcore::Device)]
self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) != 0
}
- fn is_legacy_mode(&self) -> bool {
- self.regs.borrow().config & (1 << HPET_CFG_LEG_RT_SHIFT) != 0
- }
-
- fn is_hpet_enabled(&self) -> bool {
- self.regs.borrow().config & (1 << HPET_CFG_ENABLE_SHIFT) != 0
- }
-
- fn is_timer_int_active(&self, index: usize) -> bool {
- self.regs.borrow().int_status & (1 << index) != 0
- }
-
fn get_ticks(&self) -> u64 {
ns_to_ticks(CLOCK_VIRTUAL.get_ns() + self.hpet_offset.get())
}
}
fn handle_legacy_irq(&self, irq: u32, level: u32) {
+ let regs = self.regs.borrow();
if irq == HPET_LEGACY_PIT_INT {
- if !self.is_legacy_mode() {
+ if !regs.is_legacy_mode() {
self.irqs[0].set(level != 0);
}
} else {
self.rtc_irq_level.set(level);
- if !self.is_legacy_mode() {
+ if !regs.is_legacy_mode() {
self.irqs[RTC_ISA_IRQ].set(level != 0);
}
}
/// Main Counter Value Register
fn set_counter_reg(&self, shift: u32, len: u32, val: u64) {
- if self.is_hpet_enabled() {
+ let mut regs = self.regs.borrow_mut();
+ if regs.is_hpet_enabled() {
// HPET spec says that writes to this register should only be
// done while the counter is halted. So this is an undefined
// behavior. There's no need to forbid it, but when HPET is
// not be changed as well).
trace::trace_hpet_ram_write_counter_write_while_enabled();
}
- let mut regs = self.regs.borrow_mut();
regs.counter = regs.counter.deposit(shift, len, val);
}
Global(CFG) => self.regs.borrow().config,
Global(INT_STATUS) => self.regs.borrow().int_status,
Global(COUNTER) => {
- let cur_tick = if self.is_hpet_enabled() {
+ let regs = self.regs.borrow();
+ let cur_tick = if regs.is_hpet_enabled() {
self.get_ticks()
} else {
- self.regs.borrow().counter
+ regs.counter
};
trace::trace_hpet_ram_read_reading_counter((addr & 4) as u8, cur_tick);
}
fn pre_save(&self) -> Result<(), migration::Infallible> {
- if self.is_hpet_enabled() {
- self.regs.borrow_mut().counter = self.get_ticks();
+ let mut regs = self.regs.borrow_mut();
+ if regs.is_hpet_enabled() {
+ regs.counter = self.get_ticks();
}
/*
}
fn is_offset_needed(&self) -> bool {
- self.is_hpet_enabled() && self.hpet_offset_saved
+ self.regs.borrow().is_hpet_enabled() && self.hpet_offset_saved
}
fn validate_num_timers(&self, _version_id: u8) -> bool {