#define UNSPECIFIED_COLOR_FORMAT 5
#define NUM_SYS_INIT_PACKETS 8
+#define NUM_COMV_AV1 18
#define SYS_INIT_PKT_SIZE (sizeof(struct iris_hfi_header) + \
NUM_SYS_INIT_PACKETS * (sizeof(struct iris_hfi_packet) + sizeof(u32)))
case BUF_COMV:
case BUF_NON_COMV:
case BUF_LINE:
+ case BUF_PARTIAL:
return HFI_PORT_BITSTREAM;
case BUF_OUTPUT:
case BUF_DPB:
case V4L2_PIX_FMT_H264:
profile = inst->fw_caps[PROFILE_H264].value;
break;
+ case V4L2_PIX_FMT_AV1:
+ profile = inst->fw_caps[PROFILE_AV1].value;
+ break;
}
inst_hfi_gen2->src_subcr_params.profile = profile;
case V4L2_PIX_FMT_H264:
level = inst->fw_caps[LEVEL_H264].value;
break;
+ case V4L2_PIX_FMT_AV1:
+ level = inst->fw_caps[LEVEL_AV1].value;
+ break;
}
inst_hfi_gen2->src_subcr_params.level = level;
static int iris_hfi_gen2_set_tier(struct iris_inst *inst, u32 plane)
{
- struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
+ struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
u32 tier = inst->fw_caps[TIER].value;
+ tier = (inst->codec == V4L2_PIX_FMT_AV1) ? inst->fw_caps[TIER_AV1].value :
+ inst->fw_caps[TIER].value;
inst_hfi_gen2->src_subcr_params.tier = tier;
return iris_hfi_gen2_session_set_property(inst,
sizeof(u32));
}
+static int iris_hfi_gen2_set_film_grain(struct iris_inst *inst, u32 plane)
+{
+ u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
+ struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
+ u32 film_grain = inst->fw_caps[FILM_GRAIN].value;
+
+ inst_hfi_gen2->src_subcr_params.film_grain = film_grain;
+
+ return iris_hfi_gen2_session_set_property(inst,
+ HFI_PROP_AV1_FILM_GRAIN_PRESENT,
+ HFI_HOST_FLAGS_NONE,
+ port,
+ HFI_PAYLOAD_U32_ENUM,
+ &film_grain,
+ sizeof(u32));
+}
+
+static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane)
+{
+ u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
+ struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
+ u32 super_block = inst->fw_caps[SUPER_BLOCK].value;
+
+ inst_hfi_gen2->src_subcr_params.super_block = super_block;
+
+ return iris_hfi_gen2_session_set_property(inst,
+ HFI_PROP_AV1_SUPER_BLOCK_ENABLED,
+ HFI_HOST_FLAGS_NONE,
+ port,
+ HFI_PAYLOAD_U32_ENUM,
+ &super_block,
+ sizeof(u32));
+}
+
static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane)
{
const struct iris_platform_data *pdata = inst->core->iris_platform_data;
{HFI_PROP_LINEAR_STRIDE_SCANLINE, iris_hfi_gen2_set_linear_stride_scanline },
{HFI_PROP_TIER, iris_hfi_gen2_set_tier },
{HFI_PROP_FRAME_RATE, iris_hfi_gen2_set_frame_rate },
+ {HFI_PROP_AV1_FILM_GRAIN_PRESENT, iris_hfi_gen2_set_film_grain },
+ {HFI_PROP_AV1_SUPER_BLOCK_ENABLED, iris_hfi_gen2_set_super_block },
+ {HFI_PROP_OPB_ENABLE, iris_hfi_gen2_set_opb_enable },
};
if (inst->domain == DECODER) {
} else if (inst->codec == V4L2_PIX_FMT_VP9) {
config_params = pdata->dec_input_config_params_vp9;
config_params_size = pdata->dec_input_config_params_vp9_size;
+ } else if (inst->codec == V4L2_PIX_FMT_AV1) {
+ config_params = pdata->dec_input_config_params_av1;
+ config_params_size = pdata->dec_input_config_params_av1_size;
} else {
return -EINVAL;
}
break;
case V4L2_PIX_FMT_VP9:
codec = HFI_CODEC_DECODE_VP9;
+ break;
+ case V4L2_PIX_FMT_AV1:
+ codec = HFI_CODEC_DECODE_AV1;
}
iris_hfi_gen2_packet_session_property(inst,
change_param_size =
core->iris_platform_data->dec_input_config_params_vp9_size;
break;
+ case V4L2_PIX_FMT_AV1:
+ change_param = core->iris_platform_data->dec_input_config_params_av1;
+ change_param_size =
+ core->iris_platform_data->dec_input_config_params_av1_size;
+ break;
}
payload[0] = HFI_MODE_PORT_SETTINGS_CHANGE;
payload_size = sizeof(u32);
payload_type = HFI_PAYLOAD_U32;
break;
+ case HFI_PROP_AV1_FILM_GRAIN_PRESENT:
+ payload[0] = subsc_params.film_grain;
+ payload_size = sizeof(u32);
+ payload_type = HFI_PAYLOAD_U32;
+ break;
+ case HFI_PROP_AV1_SUPER_BLOCK_ENABLED:
+ payload[0] = subsc_params.super_block;
+ payload_size = sizeof(u32);
+ payload_type = HFI_PAYLOAD_U32;
+ break;
default:
prop_type = 0;
ret = -EINVAL;
subscribe_prop_size =
core->iris_platform_data->dec_output_prop_vp9_size;
break;
+ case V4L2_PIX_FMT_AV1:
+ subcribe_prop = core->iris_platform_data->dec_output_prop_av1;
+ subscribe_prop_size =
+ core->iris_platform_data->dec_output_prop_av1_size;
+ break;
}
}
return HFI_BUFFER_ARP;
case BUF_VPSS:
return HFI_BUFFER_VPSS;
+ case BUF_PARTIAL:
+ return HFI_BUFFER_PARTIAL_DATA;
default:
return 0;
}
u32 num_comv;
caps = core->iris_platform_data->inst_caps;
- num_comv = caps->num_comv;
+
+ /*
+ * AV1 needs more comv buffers than other codecs.
+ * Update accordingly.
+ */
+ num_comv = (inst->codec == V4L2_PIX_FMT_AV1) ?
+ NUM_COMV_AV1 : caps->num_comv;
return core->hfi_ops->session_set_property(inst,
HFI_PROP_COMV_BUFFER_COUNT,
.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
.set = iris_set_u32_enum,
},
+ {
+ .cap_id = PROFILE_AV1,
+ .min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
+ .max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN),
+ .value = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
{
.cap_id = PROFILE_VP9,
.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
.set = iris_set_u32_enum,
},
+ {
+ .cap_id = LEVEL_AV1,
+ .min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0,
+ .max = V4L2_MPEG_VIDEO_AV1_LEVEL_6_1,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_0) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_2) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_3) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_0) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_2) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_3) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_0) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_1) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_2) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_3) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_0) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_1) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_2) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_3) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_0) |
+ BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_1),
+ .value = V4L2_MPEG_VIDEO_AV1_LEVEL_6_1,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
{
.cap_id = TIER,
.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
.set = iris_set_u32_enum,
},
+ {
+ .cap_id = TIER_AV1,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ .hfi_id = HFI_PROP_TIER,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = DRAP,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ .hfi_id = HFI_PROP_AV1_DRAP_CONFIG,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = FILM_GRAIN,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ .hfi_id = HFI_PROP_AV1_FILM_GRAIN_PRESENT,
+ .flags = CAP_FLAG_VOLATILE,
+ },
+ {
+ .cap_id = SUPER_BLOCK,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ .hfi_id = HFI_PROP_AV1_SUPER_BLOCK_ENABLED,
+ },
+ {
+ .cap_id = ENH_LAYER_COUNT,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ .hfi_id = HFI_PROP_AV1_OP_POINT,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
{
.cap_id = INPUT_BUF_HOST_MAX_COUNT,
.min = DEFAULT_MAX_HOST_BUF_COUNT,
HFI_PROP_LEVEL,
};
+static const u32 sm8550_vdec_input_config_param_av1[] = {
+ HFI_PROP_BITSTREAM_RESOLUTION,
+ HFI_PROP_CROP_OFFSETS,
+ HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
+ HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT,
+ HFI_PROP_PROFILE,
+ HFI_PROP_LEVEL,
+ HFI_PROP_TIER,
+ HFI_PROP_AV1_FILM_GRAIN_PRESENT,
+ HFI_PROP_AV1_SUPER_BLOCK_ENABLED,
+ HFI_PROP_SIGNAL_COLOR_INFO,
+};
+
static const u32 sm8550_venc_input_config_params[] = {
HFI_PROP_COLOR_FORMAT,
HFI_PROP_RAW_RESOLUTION,
HFI_PROP_PICTURE_TYPE,
};
+static const u32 sm8550_vdec_subscribe_output_properties_av1[] = {
+ HFI_PROP_PICTURE_TYPE,
+ HFI_PROP_WORST_COMPRESSION_RATIO,
+ HFI_PROP_WORST_COMPLEXITY_FACTOR,
+};
+
static const u32 sm8550_dec_ip_int_buf_tbl[] = {
BUF_BIN,
BUF_COMV,
BUF_NON_COMV,
BUF_LINE,
+ BUF_PARTIAL,
};
static const u32 sm8550_dec_op_int_buf_tbl[] = {
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
+
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
sm8550_vdec_input_config_param_vp9,
.dec_input_config_params_vp9_size =
ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
.dec_output_config_params =
sm8550_vdec_output_config_params,
.dec_output_config_params_size =
.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
.dec_output_prop_vp9_size =
ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),