net: pcs: xpcs: mask readl() return value to 16 bits

readl() returns 32-bit value but Clause 22/45 registers are 16-bit wide.
Masking with 0xFFFF avoids using garbage upper bits.

Signed-off-by: Jack Ping CHNG <jchng@maxlinear.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/20250716030349.3796806-1-jchng@maxlinear.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c
index 137d91038fb477c075cc873962cf99187de0a71b..9e1ccc319a1d926f29b63a074cbdb92b1e48fbe6 100644 (file)
--- a/drivers/net/pcs/pcs-xpcs-plat.c
+++ b/drivers/net/pcs/pcs-xpcs-plat.c
@@ -66,7 +66,7 @@ static int xpcs_mmio_read_reg_indirect(struct dw_xpcs_plat *pxpcs,
        switch (pxpcs->reg_width) {
        case 4:
                writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2));
-               ret = readl(pxpcs->reg_base + (ofs << 2));
+               ret = readl(pxpcs->reg_base + (ofs << 2)) & 0xffff;
                break;
        default:
                writew(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 1));
@@ -124,7 +124,7 @@ static int xpcs_mmio_read_reg_direct(struct dw_xpcs_plat *pxpcs,
 
        switch (pxpcs->reg_width) {
        case 4:
-               ret = readl(pxpcs->reg_base + (csr << 2));
+               ret = readl(pxpcs->reg_base + (csr << 2)) & 0xffff;
                break;
        default:
                ret = readw(pxpcs->reg_base + (csr << 1));