RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vadd.vv to the
vadd.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR, it will:

* The pattern matching will be active by default.
* The cost of GR2VR will be added to the total cost of pattern, aka:
  vec_dup cost = gr2vr_cost
  vadd.vv v, (vec_dup (x)) = gr2vr_cost + 1

Then the late-combine will take action if the cost of GR2VR is zero,
and reject the combination if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, OP)                                        \
  void                                                                \
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {                                                                   \
    for (unsigned i = 0; i < n; i++)                                  \
      out[i] = in[i] OP x;                                            \
  }

  DEF_VX_BINARY(int32_t, +)

Before this patch:
  10   │ test_binary_vx_add:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma // Deleted if GR2VR cost zero
  13   │     vmv.v.x v2,a2                // Ditto.
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vadd.vv v1,v2,v1
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  10   │ test_binary_vx_add:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vadd.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*<optab>_vx_<mode>): Add new
	combine to convert vec_duplicate + vadd.vv to vaddvx on GR2VR
	cost.
	* config/riscv/riscv.cc (riscv_rtx_costs): Take care of the cost
	when vec_dup and vadd v, vec_dup(x).
	* config/riscv/vector-iterators.md: Add new iterator for vx.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 0c3b0cc7e05f8d57d2cbb5b8359648c0c89e2900..7cf7e8a92ba1080690a0de87273455e0d50add86 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1673,3 +1673,26 @@
     DONE;
   }
   [(set_attr "type" "vandn")])
+
+
+;; =============================================================================
+;; Combine vec_duplicate + op.vv to op.vx
+;; Include
+;; - vadd.vx
+;; =============================================================================
+(define_insn_and_split "*<optab>_vx_<mode>"
+ [(set (match_operand:V_VLSI    0 "register_operand")
+       (any_int_binop_no_shift_vx:V_VLSI
+        (vec_duplicate:V_VLSI
+          (match_operand:<VEL> 1 "register_operand"))
+        (match_operand:V_VLSI  2 "<binop_rhs2_predicate>")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    rtx ops[] = {operands[0], operands[2], operands[1]};
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<CODE>, <MODE>mode),
+                                  riscv_vector::BINARY_OP, ops);
+  }
+  [(set_attr "type" "vialu")])

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 42d501a1291befc4fd4f81603202991a93bc7c77..3ee88db24fa5870f651b3e50c20d06fcdab4a247 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3863,7 +3863,40 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
      Cost Model need to be well analyzed and supported in the future. */
   if (riscv_v_ext_mode_p (mode))
     {
-      *total = COSTS_N_INSNS (1);
+      int gr2vr_cost = get_gr2vr_cost ();
+
+      switch (outer_code)
+       {
+       case SET:
+         {
+           switch (GET_CODE (x))
+             {
+             case VEC_DUPLICATE:
+               *total = gr2vr_cost * COSTS_N_INSNS (1);
+               break;
+             case PLUS:
+               {
+                 rtx op_0 = XEXP (x, 0);
+                 rtx op_1 = XEXP (x, 1);
+
+                 if (GET_CODE (op_0) == VEC_DUPLICATE
+                     || GET_CODE (op_1) == VEC_DUPLICATE)
+                   *total = (gr2vr_cost + 1) * COSTS_N_INSNS (1);
+                 else
+                   *total = COSTS_N_INSNS (1);
+               }
+               break;
+             default:
+               *total = COSTS_N_INSNS (1);
+               break;
+             }
+         }
+         break;
+       default:
+         *total = COSTS_N_INSNS (1);
+         break;
+       }
+
       return true;
     }
 

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index b4c869094f37d7e0c8697ac9418592de9c6dd0e6..eae33409cb052a6515204478be60e1cbeb5dbc0f 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4041,6 +4041,10 @@
   smax umax smin umin mult div udiv mod umod
 ])
 
+(define_code_iterator any_int_binop_no_shift_vx [
+  plus
+])
+
 (define_code_iterator any_int_unop [neg not])
 
 (define_code_iterator any_commutative_binop [plus and ior xor