]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r8a779a0: Fix PMU interrupt
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thu, 25 Mar 2021 04:19:49 +0000 (13:19 +0900)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 14 May 2021 08:49:42 +0000 (10:49 +0200)
[ Upstream commit bbbf6db5a0b56199702bb225132831bced2eee41 ]

Should use PPI No.7 for the PMU. Otherwise, the perf command didn't
show any information.

Fixes: 834c310f5418 ("arm64: dts: renesas: Add Renesas R8A779A0 SoC support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210325041949.925777-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/renesas/r8a779a0.dtsi

index 6cf77ce9aa9372ceea92eaeb013d8ea2594b78fb..86ec32a919d296a983b7091940ff9489579c76d2 100644 (file)
 
        pmu_a76 {
                compatible = "arm,cortex-a76-pmu";
-               interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
        /* External SCIF clock - to be overridden by boards that provide it */