]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter
authorAurelien Jarno <aurelien@aurel32.net>
Thu, 26 Mar 2026 18:35:34 +0000 (19:35 +0100)
committerYixun Lan <dlan@kernel.org>
Fri, 27 Mar 2026 02:17:28 +0000 (02:17 +0000)
Enable the two PCIe controller along with and their associated PHY. They
are routed to the M.2 M-key connector and to the PCIe x8 slot.

Add an always-on regulator sourcing 3.3V from the DC-IN input, to power
the PCIe ports.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts

index 8eeaf2631b7195e3635a15a936cdae9be036e858..afaad59e6bce22d1e55e7e6b96b9095e135a05bb 100644 (file)
                };
        };
 
+       pcie_vcc_3v3: regulator-pcie-vcc3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "pcie_vcc3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               vin-supply = <&reg_dc_in>;
+       };
+
        reg_dc_in: regulator-dc-in-12v {
                compatible = "regulator-fixed";
                regulator-name = "dc_in_12v";
        };
 };
 
+&pcie1_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_3_cfg>;
+       status = "okay";
+};
+
+&pcie1_port {
+       phys = <&pcie1_phy>;
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie1 {
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+       status = "okay";
+};
+
+&pcie2_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_4_cfg>;
+       status = "okay";
+};
+
+&pcie2_port {
+       phys = <&pcie2_phy>;
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie2 {
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+       status = "okay";
+};
+
 &qspi {
        pinctrl-names = "default";
        pinctrl-0 = <&qspi_cfg>;