Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ae04c97ce921aeb6851b69f3a49257531881e725..954b2d4ec3825890fe76fba882b7d7fc293ace86 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2025-06-20  Jeff Law  <jlaw@ventanamicro.com>
+
+       Backported from master:
+       2025-05-05  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR target/119971
+       * config/riscv/bitmanip.md (rotation with masked count): Rewrite
+       as define_insn patterns.  Fix formatting.
+       * config/riscv/riscv.md (shift with masked count): Similarly.
+
 2025-06-19  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 48356deb7cfbae5c4788ac0cf59136dc986db0c9..51152be9a3a6a8c8ebe3eda8a18da489c59db066 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250620
+20250621

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d3e3583d260d757a59d81fe359fdce28edac6684..44a10f8a9d1b2726ad008a2761bdf2e75a79b4d1 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2025-06-20  Jeff Law  <jlaw@ventanamicro.com>
+
+       Backported from master:
+       2025-05-05  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR target/119971
+       * gcc.target/riscv/pr119971.c: New test.
+       * gcc.target/riscv/zbb-rol-ror-03.c: Adjust test slightly.
+
 2025-06-19  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from master: