Currently, we manually define PCI bridge nodes in devices that use
PCI cards, etc.
But since we will need to rework this for 6.12 anyway since upstream added
the PCIe bridge nodes[1][2] lets backport it now.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v6.12.28&id=
ed3893f6f9b800ca774f63810c5f8838bc7cee78
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq6018.dtsi?h=v6.12.28&id=
52358c64937e982d3cdcf64be58f08f30d8e518c
Link: https://github.com/openwrt/openwrt/pull/18789
Signed-off-by: Robert Marko <robimarko@gmail.com>
--- /dev/null
+From ed3893f6f9b800ca774f63810c5f8838bc7cee78 Mon Sep 17 00:00:00 2001
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Date: Thu, 21 Mar 2024 16:46:35 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Add PCIe bridge node
+
+On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
+for each controller instance. Hence, add a node to represent the bridge.
+
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -878,6 +878,16 @@
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
++
++ pcie@0 {
++ device_type = "pci";
++ reg = <0x0 0x0 0x0 0x0 0x0>;
++ bus-range = <0x01 0xff>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++ ranges;
++ };
+ };
+
+ pcie0: pci@20000000 {
+@@ -943,6 +953,16 @@
+ "axi_m_sticky",
+ "axi_s_sticky";
+ status = "disabled";
++
++ pcie@0 {
++ device_type = "pci";
++ reg = <0x0 0x0 0x0 0x0 0x0>;
++ bus-range = <0x01 0xff>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++ ranges;
++ };
+ };
+ };
+
--- /dev/null
+From 52358c64937e982d3cdcf64be58f08f30d8e518c Mon Sep 17 00:00:00 2001
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Date: Thu, 21 Mar 2024 16:46:36 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Add PCIe bridge node
+
+On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
+for each controller instance. Hence, add a node to represent the bridge.
+
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -911,6 +911,16 @@
+ "axi_s_sticky";
+
+ status = "disabled";
++
++ pcie@0 {
++ device_type = "pci";
++ reg = <0x0 0x0 0x0 0x0 0x0>;
++ bus-range = <0x01 0xff>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++ ranges;
++ };
+ };
+ };
+
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 142
-@@ -927,8 +926,7 @@
+@@ -937,8 +936,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
-@@ -967,6 +998,56 @@
- "axi_s_sticky";
- status = "disabled";
+@@ -987,6 +1018,56 @@
+ ranges;
+ };
};
+
+ q6v5_wcss: q6v5_wcss@cd00000 {
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -1048,6 +1048,117 @@
+@@ -1068,6 +1068,117 @@
};
};
};
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -1166,6 +1166,7 @@
+@@ -1176,6 +1176,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";