]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
qualcommax: ipq807x, ipq60xx: backport DTS PCIe bridge node
authorRobert Marko <robimarko@gmail.com>
Mon, 12 May 2025 17:57:41 +0000 (19:57 +0200)
committerRobert Marko <robimarko@gmail.com>
Tue, 13 May 2025 17:58:22 +0000 (19:58 +0200)
Currently, we manually define PCI bridge nodes in devices that use
PCI cards, etc.

But since we will need to rework this for 6.12 anyway since upstream added
the PCIe bridge nodes[1][2] lets backport it now.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v6.12.28&id=ed3893f6f9b800ca774f63810c5f8838bc7cee78
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq6018.dtsi?h=v6.12.28&id=52358c64937e982d3cdcf64be58f08f30d8e518c

Link: https://github.com/openwrt/openwrt/pull/18789
Signed-off-by: Robert Marko <robimarko@gmail.com>
target/linux/qualcommax/patches-6.6/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch [new file with mode: 0644]
target/linux/qualcommax/patches-6.6/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch [new file with mode: 0644]
target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch

diff --git a/target/linux/qualcommax/patches-6.6/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch b/target/linux/qualcommax/patches-6.6/0049-v6.10-arm64-dts-qcom-ipq8074-Add-PCIe-bridge-node.patch
new file mode 100644 (file)
index 0000000..8a27278
--- /dev/null
@@ -0,0 +1,52 @@
+From ed3893f6f9b800ca774f63810c5f8838bc7cee78 Mon Sep 17 00:00:00 2001
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Date: Thu, 21 Mar 2024 16:46:35 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Add PCIe bridge node
+
+On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
+for each controller instance. Hence, add a node to represent the bridge.
+
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -878,6 +878,16 @@
+                                     "ahb",
+                                     "axi_m_sticky";
+                       status = "disabled";
++
++                      pcie@0 {
++                              device_type = "pci";
++                              reg = <0x0 0x0 0x0 0x0 0x0>;
++                              bus-range = <0x01 0xff>;
++
++                              #address-cells = <3>;
++                              #size-cells = <2>;
++                              ranges;
++                      };
+               };
+               pcie0: pci@20000000 {
+@@ -943,6 +953,16 @@
+                                     "axi_m_sticky",
+                                     "axi_s_sticky";
+                       status = "disabled";
++
++                      pcie@0 {
++                              device_type = "pci";
++                              reg = <0x0 0x0 0x0 0x0 0x0>;
++                              bus-range = <0x01 0xff>;
++
++                              #address-cells = <3>;
++                              #size-cells = <2>;
++                              ranges;
++                      };
+               };
+       };
diff --git a/target/linux/qualcommax/patches-6.6/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch b/target/linux/qualcommax/patches-6.6/0050-v6.10-arm64-dts-qcom-ipq6018-Add-PCIe-bridge-node.patch
new file mode 100644 (file)
index 0000000..e831cd4
--- /dev/null
@@ -0,0 +1,35 @@
+From 52358c64937e982d3cdcf64be58f08f30d8e518c Mon Sep 17 00:00:00 2001
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Date: Thu, 21 Mar 2024 16:46:36 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: Add PCIe bridge node
+
+On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
+for each controller instance. Hence, add a node to represent the bridge.
+
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -911,6 +911,16 @@
+                                     "axi_s_sticky";
+                       status = "disabled";
++
++                      pcie@0 {
++                              device_type = "pci";
++                              reg = <0x0 0x0 0x0 0x0 0x0>;
++                              bus-range = <0x01 0xff>;
++
++                              #address-cells = <3>;
++                              #size-cells = <2>;
++                              ranges;
++                      };
+               };
+       };
index 24f5711373ae4b3014b5b2938a18086f31d194cd..7c3dffe9206222c660952a7a95712ab6e7d9cc0e 100644 (file)
@@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &intc 0 0 142
-@@ -927,8 +926,7 @@
+@@ -937,8 +936,7 @@
                        ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
                                 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
  
index 0988cb1a2340ccb12c9b91c95978a563ede4aa9e..01a513de14db63d2b0fe51605e499a73f09e227c 100644 (file)
@@ -61,9 +61,9 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
                spmi_bus: spmi@200f000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0x0200f000 0x001000>,
-@@ -967,6 +998,56 @@
-                                     "axi_s_sticky";
-                       status = "disabled";
+@@ -987,6 +1018,56 @@
+                               ranges;
+                       };
                };
 +
 +              q6v5_wcss: q6v5_wcss@cd00000 {
index e1b31078f344c3263dc92c3fea695b47f2f1c0f1..35f970dc2a9e69c3783b119f87c39f32e3015576 100644 (file)
@@ -15,7 +15,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -1048,6 +1048,117 @@
+@@ -1068,6 +1068,117 @@
                                };
                        };
                };
index d29b6826bb5b2ee5171faed3b563b9e2c560d984..3fc8cbd1204989074585023054c7848e884043f4 100644 (file)
@@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -1166,6 +1166,7 @@
+@@ -1176,6 +1176,7 @@
  
                wcss_smp2p_out: master-kernel {
                        qcom,entry-name = "master-kernel";