#include "iris_platform_sc7280.h"
#include "iris_platform_sm8250.h"
+static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = {
+ .firmware_data = &iris_hfi_gen1_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .fwname = "qcom/vpu/vpu20_p1.mbn",
+};
+
+static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = {
+ .firmware_data = &iris_hfi_gen1_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .fwname = "qcom/vpu/vpu20_p4.mbn",
+};
+
static struct iris_fmt iris_fmts_vpu2_dec[] = {
[IRIS_FMT_H264] = {
.pixfmt = V4L2_PIX_FMT_H264,
};
const struct iris_platform_data sc7280_data = {
- .firmware_data = &iris_hfi_gen1_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
+ .firmware_desc = &iris_vpu20_p1_gen1_desc,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = iris_icc_info_vpu2,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
.opp_clk_tbl = sc7280_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu20_p1.mbn",
.inst_iris_fmts = iris_fmts_vpu2_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
.inst_caps = &platform_inst_cap_vpu2,
};
const struct iris_platform_data sm8250_data = {
- .firmware_data = &iris_hfi_gen1_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
+ .firmware_desc = &iris_vpu20_p4_gen1_desc,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = iris_icc_info_vpu2,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
.opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu20_p4.mbn",
.inst_iris_fmts = iris_fmts_vpu2_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
.inst_caps = &platform_inst_cap_vpu2,
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
+static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
+};
+
+static const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .fwname = "qcom/vpu/vpu30_p4.mbn",
+};
+
+static const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .fwname = "qcom/vpu/vpu33_p4.mbn",
+};
+
+static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .fwname = "qcom/vpu/vpu35_p4.mbn",
+};
+
static struct iris_fmt iris_fmts_vpu3x_dec[] = {
[IRIS_FMT_H264] = {
.pixfmt = V4L2_PIX_FMT_H264,
* - inst_caps to platform_inst_cap_qcs8300
*/
const struct iris_platform_data qcs8300_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
+ .firmware_desc = &iris_vpu30_p4_s6_gen2_desc,
.vpu_ops = &iris_vpu3_ops,
.icc_tbl = iris_icc_info_vpu3x,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
.opp_clk_tbl = iris_opp_clk_table_vpu3x,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
.inst_iris_fmts = iris_fmts_vpu3x_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
.inst_caps = &platform_inst_cap_qcs8300,
};
const struct iris_platform_data sm8550_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
+ .firmware_desc = &iris_vpu30_p4_gen2_desc,
.vpu_ops = &iris_vpu3_ops,
.icc_tbl = iris_icc_info_vpu3x,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
.opp_clk_tbl = iris_opp_clk_table_vpu3x,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu30_p4.mbn",
.inst_iris_fmts = iris_fmts_vpu3x_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
.inst_caps = &platform_inst_cap_sm8550,
* - vpu_ops to iris_vpu33_ops
* - clk_rst_tbl to sm8650_clk_reset_table
* - controller_rst_tbl to sm8650_controller_reset_table
- * - fwname to "qcom/vpu/vpu33_p4.mbn"
*/
const struct iris_platform_data sm8650_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .firmware_desc = &iris_vpu33_p4_gen2_desc,
.vpu_ops = &iris_vpu33_ops,
.icc_tbl = iris_icc_info_vpu3x,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
.opp_clk_tbl = iris_opp_clk_table_vpu3x,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu33_p4.mbn",
.inst_iris_fmts = iris_fmts_vpu3x_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
.inst_caps = &platform_inst_cap_sm8550,
};
const struct iris_platform_data sm8750_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .firmware_desc = &iris_vpu35_p4_gen2_desc,
.vpu_ops = &iris_vpu35_ops,
.icc_tbl = iris_icc_info_vpu3x,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
.opp_clk_tbl = iris_opp_clk_table_vpu3x,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu35_p4.mbn",
.inst_iris_fmts = iris_fmts_vpu3x_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
.inst_caps = &platform_inst_cap_sm8550,