RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2...

Add asm dump check test for vec_duplicate + vdivu.vv combine to vdivu.vx,
with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vdivu.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 7e107d30191d0219c48b08fe6ca8cd413eee52ba..92fbf227d5639421f045c010b38b29cac36b1641 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index f8ffab78067a26d8c4797f9c9570624afebd8164..f487b42820eed462d4a0a82832a32adb45cf6fc2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 31d294567e8314171fa83fb9dbff0c15bca19ba2..761d25c0833a355a513446f597f19fc88054762d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 59e033401b21cf484482a74156497c140929ff95..0018bd2a31e7b4b91040f8350109c4f3183f5bcf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 9612e3f66cc4456f846481958d75a1056a7c89f1..554acacd411bda17a9db3fe0cf51ad6870ac5ba5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 964180243b47261b8255486ab90adf402d7f229f..0e74a3bfded3beed9fae2601187197296804853f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 0d173e0dbbb904822bf8a6ba2260ce82d2abce61..8e831cee6646a550b7c40e420fe56b6bb6c343b8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 931295ec0fb3bd4420dfb69626c4ca4292d75bba..dad75627904ccdf0aa2d862701dcb4de2a0480b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 24b4aa7efba19ddb50a103d89ef8d7d1f57cc82f..873fbf3da258eeda3d3f6fd0bf05d8f86e2094c6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 0c1552a2054139c82011ec96520bef410e6f3e79..cbf35e1b4fe620378a094270a7d095370221501c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 8364f19b1787ab92bfbdec747d1a3b2d54f790a2..3ccf42b9c0281a6414330c29a94156aa7e3593c3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 8a3111157ffe08b17c864761aee6c4dc1fa2b38f..50825ef9f32379b4b094ab89ea35b06ae7e085d3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, /, div)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vdivu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index ed8c56252dfd8422efd0dd520d04385d00bfc03f..5130709050ddb4a595050768bc13dac25c993ee0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -2750,4 +2750,200 @@ int64_t TEST_BINARY_DATA(int64_t, div)[][3][N] =
   },
 };
 
+uint8_t TEST_BINARY_DATA(uint8_t, div)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       4,  4,  4,  4,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       2,  2,  2,  2,
+       3,  3,  3,  3,
+    },
+  },
+  {
+    { 127 },
+    {
+       127,  127,  127,  127,
+         1,    1,    1,    1,
+       128,  128,  128,  128,
+         2,    2,    2,    2,
+    },
+    {
+         1,    1,    1,    1,
+         0,    0,    0,    0,
+         1,    1,    1,    1,
+         0,    0,    0,    0,
+    },
+  },
+  {
+    { 128 },
+    {
+       127,  127,  127,  127,
+       255,  255,  255,  255,
+       128,  128,  128,  128,
+         1,    1,    1,    1,
+    },
+    {
+         0,    0,    0,    0,
+         1,    1,    1,    1,
+         1,    1,    1,    1,
+         0,    0,    0,    0,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, div)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       4,  4,  4,  4,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       2,  2,  2,  2,
+       3,  3,  3,  3,
+    },
+  },
+  {
+    { 32767 },
+    {
+       32767,  32767,  32767,  32767,
+           1,      1,      1,      1,
+       32768,  32768,  32768,  32768,
+           2,      2,      2,      2,
+    },
+    {
+           1,      1,      1,      1,
+           0,      0,      0,      0,
+           1,      1,      1,      1,
+           0,      0,      0,      0,
+    },
+  },
+  {
+    { 32768 },
+    {
+       32767,  32767,  32767,  32767,
+       65535,  65535,  65535,  65535,
+       32768,  32768,  32768,  32768,
+           1,      1,      1,      1,
+    },
+    {
+           0,      0,      0,      0,
+           1,      1,      1,      1,
+           1,      1,      1,      1,
+           0,      0,      0,      0,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, div)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       4,  4,  4,  4,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       2,  2,  2,  2,
+       3,  3,  3,  3,
+    },
+  },
+  {
+    { 2147483647 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+                1,           1,           1,           1,
+       2147483648,  2147483648,  2147483648,  2147483648,
+                2,           2,           2,           2,
+    },
+    {
+                1,           1,           1,           1,
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+                0,           0,           0,           0,
+    },
+  },
+  {
+    { 2147483648 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       2147483648,  2147483648,  2147483648,  2147483648,
+                1,           1,           1,           1,
+    },
+    {
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+                1,           1,           1,           1,
+                0,           0,           0,           0,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, div)[][3][N] =
+{
+  {
+    { 2 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       4,  4,  4,  4,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       2,  2,  2,  2,
+       3,  3,  3,  3,
+    },
+  },
+  {
+    { 9223372036854775807ull },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                1,           1,           1,           1,
+       9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,
+                2,           2,           2,           2,
+    },
+    {
+                1,           1,           1,           1,
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+                0,           0,           0,           0,
+    },
+  },
+  {
+    { 9223372036854775808ull },
+    {
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+        9223372036854775808ull,   9223372036854775808ull,   9223372036854775808ull,   9223372036854775808ull,
+                             1,                        1,                        1,                        1,
+    },
+    {
+                             0,                        0,                        0,                        0,
+                             1,                        1,                        1,                        1,
+                             1,                        1,                        1,                        1,
+                             0,                        0,                        0,                        0,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c
new file mode 100644 (file)
index 0000000..afb848d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME div
+
+DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c
new file mode 100644 (file)
index 0000000..4acaa5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME div
+
+DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c
new file mode 100644 (file)
index 0000000..335a909
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME div
+
+DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c
new file mode 100644 (file)
index 0000000..160d362
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME div
+
+DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"