arm: [MVE intrinsics] factorize vshllbq vshlltq

Factorize vshllbq vshlltq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (mve_insn): Add vshllb, vshllt.
	(VSHLLBQ_N, VSHLLTQ_N): Remove.
	(VSHLLxQ_N): New.
	(VSHLLBQ_M_N, VSHLLTQ_M_N): Remove.
	(VSHLLxQ_M_N): New.
	* config/arm/mve.md (mve_vshllbq_n_<supf><mode>)
	(mve_vshlltq_n_<supf><mode>): Merge into ...
	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
	(mve_vshllbq_m_n_<supf><mode>, mve_vshlltq_m_n_<supf><mode>):
	Merge into ...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 207352849799e438cebbe6224dd6032ff7a559f9..e82ff0d5d9bf23444fc116087be03af29a2f3c3f 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -731,6 +731,10 @@
                 (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt")
                 (VRSHRQ_M_N_S "vrshr") (VRSHRQ_M_N_U "vrshr")
                 (VRSHRQ_N_S "vrshr") (VRSHRQ_N_U "vrshr")
+                (VSHLLBQ_M_N_S "vshllb") (VSHLLBQ_M_N_U "vshllb")
+                (VSHLLBQ_N_S "vshllb") (VSHLLBQ_N_U "vshllb")
+                (VSHLLTQ_M_N_S "vshllt") (VSHLLTQ_M_N_U "vshllt")
+                (VSHLLTQ_N_S "vshllt") (VSHLLTQ_N_U "vshllt")
                 (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl")
                 (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl")
                 (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
@@ -2133,8 +2137,7 @@
 (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
 (define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
 (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
-(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
-(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
+(define_int_iterator VSHLLxQ_N [VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_S VSHLLTQ_N_U])
 (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
 (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
 (define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
@@ -2250,8 +2253,7 @@
 (define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
 (define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
 (define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
-(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
-(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
+(define_int_iterator VSHLLxQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
 (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
 (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
 (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 2273078807b5cea28ceba5d7a1a23c0f6d308afe..98728e6f3ef69a5362658331d900f8abe9d1fe18 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1830,32 +1830,18 @@
 ])
 
 ;;
-;; [vshllbq_n_s, vshllbq_n_u])
+;; [vshllbq_n_s, vshllbq_n_u]
+;; [vshlltq_n_u, vshlltq_n_s]
 ;;
-(define_insn "mve_vshllbq_n_<supf><mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
-       (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
-                                 (match_operand:SI 2 "immediate_operand" "i")]
-        VSHLLBQ_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vshlltq_n_u, vshlltq_n_s])
-;;
-(define_insn "mve_vshlltq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
        (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
                                  (match_operand:SI 2 "immediate_operand" "i")]
-        VSHLLTQ_N))
+        VSHLLxQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4410,36 +4396,20 @@
    (set_attr "length""8")])
 
 ;;
-;; [vshllbq_m_n_u, vshllbq_m_n_s])
-;;
-(define_insn "mve_vshllbq_m_n_<supf><mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
-       (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
-                      (match_operand:MVE_3 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "immediate_operand" "i")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VSHLLBQ_M_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vshlltq_m_n_u, vshlltq_m_n_s])
+;; [vshllbq_m_n_u, vshllbq_m_n_s]
+;; [vshlltq_m_n_u, vshlltq_m_n_s]
 ;;
-(define_insn "mve_vshlltq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_3 2 "s_register_operand" "w")
                       (match_operand:SI 3 "immediate_operand" "i")
                       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VSHLLTQ_M_N))
+        VSHLLxQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])