arm64: dts: imx8mp: Add DT nodes for the two ISPs

The ISP supports both CSI and parallel interfaces, where port 0
corresponds to the former and port 1 corresponds to the latter. Since
the i.MX8MP's ISPs are connected by the parallel interface to the CSI
receiver, set them both to port 1.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d9b5c40f6460f01ae22125d6b386af793e06322b..f3531cfb0d7913c090eb68776672c658d914323a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1673,6 +1673,50 @@
                                };
                        };
 
+                       isp_0: isp@32e10000 {
+                               compatible = "fsl,imx8mp-isp";
+                               reg = <0x32e10000 0x10000>;
+                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+                               clock-names = "isp", "aclk", "hclk";
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+                               fsl,blk-ctrl = <&media_blk_ctrl 0>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@1 {
+                                               reg = <1>;
+                                       };
+                               };
+                       };
+
+                       isp_1: isp@32e20000 {
+                               compatible = "fsl,imx8mp-isp";
+                               reg = <0x32e20000 0x10000>;
+                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+                               clock-names = "isp", "aclk", "hclk";
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+                               fsl,blk-ctrl = <&media_blk_ctrl 1>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@1 {
+                                               reg = <1>;
+                                       };
+                               };
+                       };
+
                        dewarp: dwe@32e30000 {
                                compatible = "nxp,imx8mp-dw100";
                                reg = <0x32e30000 0x10000>;
@@ -1869,17 +1913,26 @@
                                clock-names = "apb", "axi", "cam1", "cam2",
                                              "disp1", "disp2", "isp", "phy";
 
+                               /*
+                                * The ISP maximum frequency is 400MHz in normal mode
+                                * and 500MHz in overdrive mode. The 400MHz operating
+                                * point hasn't been successfully tested yet, so set
+                                * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being.
+                                */
                                assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
                                                  <&clk IMX8MP_CLK_MEDIA_APB>,
                                                  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
                                                  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+                                                 <&clk IMX8MP_CLK_MEDIA_ISP>,
                                                  <&clk IMX8MP_VIDEO_PLL1>;
                                assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
                                                         <&clk IMX8MP_SYS_PLL1_800M>,
                                                         <&clk IMX8MP_VIDEO_PLL1_OUT>,
-                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>;
+                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>,
+                                                        <&clk IMX8MP_SYS_PLL2_500M>;
                                assigned-clock-rates = <500000000>, <200000000>,
-                                                      <0>, <0>, <1039500000>;
+                                                      <0>, <0>, <500000000>,
+                                                      <1039500000>;
                                #power-domain-cells = <1>;
 
                                lvds_bridge: bridge@5c {