Ensure host CPU is in the state that VEX-generated code expects prior

to running any such code.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3182

diff --git a/coregrind/x86/dispatch.S b/coregrind/x86/dispatch.S
index 6c5c4e78c1df03c5d82a35e7713ad3d330f8f0f8..7505f8c459b233fa65a23d49054a5fe6f43d7c68 100644 (file)
--- a/coregrind/x86/dispatch.S
+++ b/coregrind/x86/dispatch.S
@@ -67,12 +67,22 @@ VG_(run_innerloop):
        movl    VG_(instr_ptr_offset), %esi
        movl    (%ebp, %esi, 1), %eax
 
-       /* set host FPU mode to the default mode expected 
+       /* set host FPU control word to the default mode expected 
           by VEX-generated code. */
+       finit
        pushl   $0x037F
-       fldcw   0(%esp)
+       fldcw   (%esp)
        addl    $4, %esp
        
+       /* set host SSE control word to the default mode expected 
+          by VEX-generated code. */
+       pushl   $0x1F80
+       ldmxcsr (%esp)
+       addl    $4, %esp
+
+       /* set dir flag to known value */
+       cld
+       
        /* fall into main loop */
 
        /* Here, %eax is the only live (real) register.  The entire