RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern

We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
only ZBA provide zero_extendsidi2 instruction.

gcc/ChangeLog

	* config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
	use this pattern.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f20d527e01466b92e5a8c99bd1700be..225e5b259c1011fb441722327b2f77592ebd5674 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1311,7 +1311,7 @@
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
        (zero_extend:DI
            (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
+  "TARGET_64BIT && !TARGET_ZBA"
   "@
    #
    lwu\t%0,%1"