arm64/sysreg: Add ICH_HFGRTR_EL2

Add ICH_HFGRTR_EL2 register description.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-12-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8be5e4af4ad662d426150c52f07ae3c664cac8f6..0202b3bd3dda3bd3493fb7828323475b6d3fb9e2 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -4434,6 +4434,24 @@ Field    31:16   PhyPARTID29
 Field  15:0    PhyPARTID28
 EndSysreg
 
+Sysreg ICH_HFGRTR_EL2  3       4       12      9       4
+Res0   63:21
+Field  20      ICC_PPI_ACTIVERn_EL1
+Field  19      ICC_PPI_PRIORITYRn_EL1
+Field  18      ICC_PPI_PENDRn_EL1
+Field  17      ICC_PPI_ENABLERn_EL1
+Field  16      ICC_PPI_HMRn_EL1
+Res0   15:8
+Field  7       ICC_IAFFIDR_EL1
+Field  6       ICC_ICSR_EL1
+Field  5       ICC_PCR_EL1
+Field  4       ICC_HPPIR_EL1
+Field  3       ICC_HAPR_EL1
+Field  2       ICC_CR0_EL1
+Field  1       ICC_IDRn_EL1
+Field  0       ICC_APR_EL1
+EndSysreg
+
 Sysreg ICH_HCR_EL2     3       4       12      11      0
 Res0   63:32
 Field  31:27   EOIcount