]> git.ipfire.org Git - thirdparty/glibc.git/commitdiff
Detect Intel Goldmont and Airmont processors
authorH.J. Lu <hjl.tools@gmail.com>
Fri, 15 Apr 2016 12:22:53 +0000 (05:22 -0700)
committerH.J. Lu <hjl.tools@gmail.com>
Fri, 15 Apr 2016 12:23:06 +0000 (05:23 -0700)
Updated from the model numbers of Goldmont and Airmont processors in
Intel64 And IA-32 Processor Architectures Software Developer's Manual
Volume 3 Revision 058.

* sysdeps/x86/cpu-features.c (init_cpu_features): Detect Intel
Goldmont and Airmont processors.

ChangeLog
sysdeps/x86/cpu-features.c

index 44deb0fd26d2dfecc88d5009bf3aeef6569eaaab..0b0b5e2202c37353753e8ab99eff0432da040710 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-15   H.J. Lu  <hongjiu.lu@intel.com>
+
+       * sysdeps/x86/cpu-features.c (init_cpu_features): Detect Intel
+       Goldmont and Airmont processors.
+
 2016-04-15  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * string/string.h: Use __GNUC_PREREQ(3,4) for bits/string2.h.
index 963b84591687e08bea6917077c6bd99954d344a0..a5fa81f709f34a461eed87d5e79faf6dfa576ea3 100644 (file)
@@ -140,6 +140,14 @@ init_cpu_features (struct cpu_features *cpu_features)
              cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
                |= bit_arch_Prefer_No_VZEROUPPER;
 
+           case 0x5c:
+           case 0x5f:
+             /* Unaligned load versions are faster than SSSE3
+                on Goldmont.  */
+
+           case 0x4c:
+             /* Airmont is a die shrink of Silvermont.  */
+
            case 0x37:
            case 0x4a:
            case 0x4d: