perf/x86/intel: Enable auto counter reload for DMR

commit aa4384bc8f4360167f3c3d5322121fe892289ea2 upstream.

Panther cove µarch starts to support auto counter reload (ACR), but the
static_call intel_pmu_enable_acr_event() is not updated for the Panther
Cove µarch used by DMR. It leads to the auto counter reload is not
really enabled on DMR.

Update static_call intel_pmu_enable_acr_event() in intel_pmu_init_pnc().

Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260430002558.712334-5-dapeng1.mi@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index d097ebb7bb88eaa447f0f07650f6b2a5838af091..d8ac015f5fdbcf009cdd88136a4627e5501a6af5 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -7525,6 +7525,7 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
        hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
        hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
        hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
+       static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
 }
 
 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)