vex_state->guest_R14 = 0;
vex_state->guest_R15 = 0;
- vex_state->guest_CC_OP = 999;//X86G_CC_OP_COPY; // XXX ???
+ vex_state->guest_CC_OP = AMD64G_CC_OP_COPY;
vex_state->guest_CC_DEP1 = 0;
vex_state->guest_CC_DEP2 = 0;
vex_state->guest_CC_NDEP = 0;
if (0 && (n_resteers & 0xFF) == 0)
vex_printf("resteer[%d,%d] to %p (delta = %d)\n",
n_resteers, d_resteers,
- (void*)(UInt)(guest_next), delta);
+ ULong_to_Ptr(guest_next), delta);
break;
}
}
if (0 && (n_resteers & 0xFF) == 0)
vex_printf("resteer[%d,%d] to %p (delta = %d)\n",
n_resteers, d_resteers,
- (void*)(UInt)(guest_next), delta);
+ ULong_to_Ptr(guest_next), delta);
break;
}
}
ULong x86g_loadF80le ( UInt addrU )
{
ULong f64;
- convert_f80le_to_f64le ( (UChar*)addrU, (UChar*)&f64 );
+ convert_f80le_to_f64le ( (UChar*)ULong_to_Ptr(addrU), (UChar*)&f64 );
return f64;
}
/* DIRTY HELPER (writes guest memory) */
void x86g_storeF80le ( UInt addrU, ULong f64 )
{
- convert_f64le_to_f80le( (UChar*)&f64, (UChar*)addrU );
+ convert_f64le_to_f80le( (UChar*)&f64, (UChar*)ULong_to_Ptr(addrU) );
}
if (0 && (n_resteers & 0xFF) == 0)
vex_printf("resteer[%d,%d] to %p (delta = %d)\n",
n_resteers, d_resteers,
- (void*)(UInt)(guest_next), delta);
+ ULong_to_Ptr(guest_next), delta);
break;
}
}
if (i->Ain.Goto.jk != Ijk_Boring) {
vex_printf("movl $");
ppIRJumpKind(i->Ain.Goto.jk);
- vex_printf(",%%rbp ; ");
+ vex_printf(",%%ebp ; ");
}
vex_printf("movq ");
ppAMD64RI(i->Ain.Goto.dst);
Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i )
{
- UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
+ UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
//..
//.. UInt xtra;
UChar* p = &buf[0];
/* Get the destination address into %rax */
if (i->Ain.Goto.dst->tag == Ari_Imm) {
- /* movl $immediate, %eax ; ret */
- *p++ = 0xB8;
+ /* movl sign-ext($immediate), %rax ; ret */
+ *p++ = 0x48;
+ *p++ = 0xC7;
+ *p++ = 0xC0;
p = emit32(p, i->Ain.Goto.dst->Ari.Imm.imm32);
} else {
vassert(i->Ain.Goto.dst->tag == Ari_Reg);
static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
static AMD64CondCode iselCondCode ( ISelEnv* env, IRExpr* e );
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
+//static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
+//static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
+//static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
+//static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+//static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
+//static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
/*---------------------------------------------------------*/
//.. /* DO NOT CALL THIS DIRECTLY */
//.. static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
//.. {
-//..
-//.. # define REQUIRE_SSE1 \
-//.. do { if (env->subarch == VexSubArchX86_sse0) \
-//.. goto vec_fail; \
-//.. } while (0)
-//..
-//.. # define REQUIRE_SSE2 \
-//.. do { if (env->subarch == VexSubArchX86_sse0 \
-//.. || env->subarch == VexSubArchX86_sse1) \
-//.. goto vec_fail; \
-//.. } while (0)
-//..
+#if 0
+# define REQUIRE_SSE1 \
+ do { if (env->subarch == VexSubArchX86_sse0) \
+ goto vec_fail; \
+ } while (0)
+
+# define REQUIRE_SSE2 \
+ do { if (env->subarch == VexSubArchX86_sse0 \
+ || env->subarch == VexSubArchX86_sse1) \
+ goto vec_fail; \
+ } while (0)
+#endif
//.. Bool arg1isEReg = False;
//.. X86SseOp op = Xsse_INVALID;
//.. IRType ty = typeOfIRExpr(env->type_env,e);
parameters. */
vassert(sizeof(void*) == 4);
- addInstr(env, X86Instr_Call( cc, (UInt)cee->addr, cee->regparms));
+ addInstr(env, X86Instr_Call( cc, (UInt)Ptr_to_ULong(cee->addr),
+ cee->regparms));
if (n_arg_ws > 0)
add_to_esp(env, 4*n_arg_ws);
}
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32
- e->Iex.Binop.arg2->Iex.Const.con->Ico.U32)));
break;
+
case Iop_Add32:
e2 = IRExpr_Const(IRConst_U32(
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32
+ e->Iex.Binop.arg2->Iex.Const.con->Ico.U32)));
break;
+ case Iop_Add64:
+ e2 = IRExpr_Const(IRConst_U64(
+ (e->Iex.Binop.arg1->Iex.Const.con->Ico.U64
+ + e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)));
+ break;
+
case Iop_Xor32:
e2 = IRExpr_Const(IRConst_U32(
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32