RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

This patch fixes ICE mentioned on PR112851 and PR112852.
Actually these ICEs happens many times in full coverage testing.

The ICE happens on:

bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
   84 | }
      | ^
0x11a7271 partial_subreg_p(machine_mode, machine_mode)
        ../../../../gcc/gcc/rtl.h:3187

gcc_checking_assert (ordered_p (outer_prec, inner_prec));

outer_prec is the PRECISION of RVVM1SImode
inner_prec is the PRECISION of V64SImode

when it is zvl512b.

outer_prec is VLA mode with size (512, 512)
inner_prec is VLS mode with size (2048, 0)

Their precision/size relationship is not certain.
So block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR, then we never reaches
the situation that comparing the precision/size between VLA size and VLS size that size > coeffs[0] of VLA mode.

Note this patch cause following regression:

FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize  scan-assembler-not vset
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize  scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2

FAIL: gcc.target/riscv/rvv/base/cpymem-1.c check-function-bodies f3
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f2
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f3

1. cpymem check FAIL should be fixed on the testcase since the test is fragile which should be robostified.

2. pr111751.c is Vector cost model issue, and I will fix it in the following patch.

For now, we should land this patch first (highest-priority) since it is fixing ICE.

	PR target/112851
	PR target/112852

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes according
	TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Add LMUL = 8 option.
	* gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f-1.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/pr112851.c: New test.
	* gcc.target/riscv/rvv/autovec/pr112852.c: New test.

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 87e50875308bf0413f780a0eb314768ecc149a4f..71cb7567f1a5933cf86a2c6dcd019215de73512e 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4051,7 +4051,21 @@ vls_mode_valid_p (machine_mode vls_mode)
     return false;
 
   if (riscv_autovec_preference == RVV_SCALABLE)
-    return true;
+    {
+      if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL
+         && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
+                        GET_MODE_PRECISION (vls_mode)))
+       /* We enable VLS modes which are aligned with TARGET_MAX_LMUL and
+          BITS_PER_RISCV_VECTOR.
+
+          e.g. When TARGET_MAX_LMUL = 1 and BITS_PER_RISCV_VECTOR = (128,128).
+          We enable VLS modes have fixed size <= 128bit.  Since ordered_p is
+          false between VLA modes with size = (128, 128) bits and VLS mode
+          with size = 128 bits, we will end up with multiple ICEs in
+          middle-end generic codes.  */
+       return false;
+      return true;
+    }
 
   if (riscv_autovec_preference == RVV_FIXED_VLMAX)
     {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c
new file mode 100644 (file)
index 0000000..ff2e4fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112851.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions" } */
+
+int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
+    safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
+    g_97_l_439;
+void g_97(int * __restrict l_437)
+{
+  for (; g_97_l_439; g_97_l_439 += 1)
+    for (char l_502 = 0; l_502 < 4; l_502++)
+      {
+        int __trans_tmp_14 = ((safe_lshift_func_int32_t_s_s_right >= 2
+                               || safe_lshift_func_int32_t_s_s_left)
+                              ? 1 : safe_lshift_func_int32_t_s_s_right);
+        long __trans_tmp_15 = __trans_tmp_14 * safe_mul_func_uint64_t_u_u_ui2;
+        unsigned short __trans_tmp_16 = -__trans_tmp_15;
+        int __trans_tmp_7
+          = (__trans_tmp_16 ^ 65535UL) - safe_sub_func_uint64_t_u_u_ui2;
+        *l_437 ^= (short)(__trans_tmp_7 ^ g_79_2);
+      }
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c
new file mode 100644 (file)
index 0000000..2d6e27e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112852.c
@@ -0,0 +1,87 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -funroll-loops -ftracer" } */
+
+struct platform_device;
+typedef unsigned long __kernel_size_t;
+typedef unsigned short __u16;
+typedef unsigned int __u32;
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef __kernel_size_t size_t;
+typedef __u32 uint32_t;
+static inline __attribute__ ((always_inline))
+uint32_t __attribute__ ((pure)) bfin_dspid (void)
+{
+    return ( {
+            uint32_t __v; __v;}
+    );
+}
+struct list_head {
+    struct list_head *next, *prev;
+};
+struct page {
+    union {
+    };
+    struct list_head lru;
+};
+struct device_driver {
+    const char *name;
+    struct module *owner;
+};
+struct fb_info {
+    struct device *dev;
+};
+struct platform_driver {
+    int (*probe) (struct platform_device *);
+    int (*remove) (struct platform_device *);
+    struct device_driver driver;
+};
+struct firmware {
+    size_t size;
+    const u8 *data;
+};
+struct metronomefb_par {
+    struct fb_info *info;
+};
+struct waveform_hdr {
+    u8 trc;
+};
+static u8 calc_cksum (int start, int end, u8 * mem)
+{
+    u8 tmp = 0;
+    int i;
+    for (i = start; i < end; i++)
+        tmp += mem[i];
+    return tmp;
+}
+extern struct waveform_hdr *wfm_hdr;
+extern int wmta;
+
+static int
+load_waveform (u8 * mem, size_t size, int m, int t, struct metronomefb_par *par)
+{
+    int tta;
+    int trn = 0;
+    int i;
+    u8 cksum;
+    int cksum_idx;
+    struct device *dev = par->info->dev;
+    for (i = 0; i <= sizeof (*wfm_hdr) + wfm_hdr->trc; i++) {
+        if (mem[i] > t) {
+            trn = i - sizeof (*wfm_hdr) - 1;
+        }
+    }
+    tta = * (mem + wmta + m * 4) & 0x00FFFFFF;
+    cksum_idx = tta + trn * 4 + 3;
+    cksum = calc_cksum (cksum_idx - 3, cksum_idx, mem);
+    if (cksum != mem[cksum_idx]) {
+        __builtin_abort();
+    }
+}
+extern struct firmware *fw_entry;
+extern struct metronomefb_par *par;
+
+int metronomefb_probe (struct platform_device *dev)
+{
+        return load_waveform ((u8 *) fw_entry->data, fw_entry->size, 3, 31, par);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
index c010c8830651079ec83980a8b78dff5a1f73e139..b9bc15f7c8267129fdc1ac0eb34f3cf29e49ed08 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
index ccbbb24ad5da00725d31299548693b0020eb7452..8c0bc201425a37a42fde3e94540dc0e8606a3eb0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
index c8caf3535536478ebdcb4bd50f560516a07cfb1e..57bbf8fbc683c6397c44a63d14cce3f843af45e7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
index 24bb7240db8d4f5f684dc625c0159ee85b797be3..18dad346464b8db8e42b7b4d47047746b5c57afd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
index cae96b3be3f51cc3733a5c19a5a309fcbafb668b..c199c330ce549baba7b264e13da257f905cfc3ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
index e2ca21e2d5b73bc549f75bd1eb2df1cef8d1734c..4737008426f21f8e3a33c6f48e6422bfe74d9e3a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
index fc38e791ecfa94ad7043cf149be0f0fd61497a4a..f61c372162e08982dfd1c6343685a6028559b5c8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
index d51922efdc9e958255a3ef727a8119fd8fdc9657..56a7cf0b9f1d35159484a25191400dec3f0c6205 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
index 8ed8f6be19ea2c82222362064faf1bdb42309fb4..de49ed82dbbc046c63a603270c4d59b20b75a704 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
index f4ce5b3c0a65cdc4d4d3b779ed3ee20d861d89c9..bed6a4784b06ede4f1043b391715d06fee69d27d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
index ff36d785bc68846ba096e1e3c2879e8bdd486b94..06ab31b3094746de85774997824bda93ed868378 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
index 754771aa69d9ecc2b1383f2a8c64f7027060eea9..c2f0e3c2fc613eb98453919b5b2aa56177a7bf74 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
index 86ce22896c5715f6f741f597f2ba180691e0aa91..77d3fed58864d4dba9820d48de59494a42abebac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
index 044752079668289508048f10b6d129887bad39be..5fae343ed49c70c5a753c4850953c0a601db4f48 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
index d0674a47a142693e48a2e2fc3440cfb39674f378..c515f0225184a7122eae0f78633543a5884db70f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
index b905c74d43b3dc7d0f8e062ba93ff0cc49579b8c..1164ab5de9fcff93571a41bf1717e6f62b187d2c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
index 5f9bc052e97611c5078de16012e4e2cdc5679592..404ef5d0e86e6f0a6fab80bec2b3a2de5899b509 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
index 753fa254002d0e759bc588c049686bc5d251e8a5..842bb630be5681fa4a75777fba64536354d7f6c7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
index e8fa54c1c127a98390322b38546d81d2e38f7f09..8f6ee81b98f274591e9f45238ec20c0234fb4b68 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
index 86a404cc2a4baec26db54383efde578574ea0d36..0f317d6cce5cb61d8db4adfcc191c643e4646aca 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
index 7bff6e3cae8de436ba92a247c5e37e35737343bd..b366a4649d875b4334deea54be265fd731fb15a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
index 1e4eca3aac64f117a378765a37518ed798368201..d35e2a44f79b83684f75f075a0c385446416a780 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
index e0a4a1f58fd8980a0862edbe96c4d7dc32179e12..ab57e89b1cdd8077fdf578277084cd780adab582 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
@@ -3,4 +3,4 @@
 
 #include "template-1.h"
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */